hb286075a1 HITACHI, hb286075a1 Datasheet - Page 11

• Manufacturer Part Number: hb286075a1
• Description: Mega Byte Flash Card
• Manufacturer: HITACHI

Configuration register specifications
This card supports four Configuration registers for the purpose of the configuration and observation of this
card.
1. Configuration Option register (Address 200H)
This register is used for the configuration of the card configuration status and for the issuing soft reset to the
card.
bit7
SRESET
Note: initial value: 00H
Name
SRESET
(HOST->)
LevlREQ
(HOST->)
INDEX
(HOST->)
INDEX bit assignment
INDEX bit
5 4 3
0 0 0
0 0 0
0 0 0
0 0 0
HB286075A1, HB286060A1, HB286045A1, HB286030A1, HB286015A1
2 1 0 Card mode
0 0 0 Memory card
0 0 1 I/O card
0 1 0 I/O card
0 1 1 I/O card
bit6
LevlREQ
R/W
R/W
R/W
R/W
Function
Setting this bit to "1", places the card in the reset state (Card Hard Reset). This
operation is equal to Hard Reset, except this bit is not cleared. Then this bit set to "0",
places the card in the reset state of Hard Reset (This bit is set to "0" by Hard Reset) .
Card configuration status is reset and the card internal initialized operation starts when
Card Hard Reset is executed, so next access to the card should be the same sequence
as the power on sequence.
This bit sets to "0" when pulse mode interrupt is selected, and "1" when level mode
interrupt is selected.
This bits is used for select operation mode of the card as follows.
When Power on, Card Hard Reset and Soft Reset, this data is "000000" for the purpose
of Memory card interface recognition.
bit5
INDEX
Task File register address
0H to FH, 400H to 7FFH
xx0H to xxFH
1F0H to 1F7H, 3F6H to 3F7H
170H to 177H, 376H to 377H
bit4
bit3
bit2
Mapping mode
memory mapped
contiguous I/O mapped
primary I/O mapped
secondary I/O mapped
bit1
bit0
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