edi88130lp ETC-unknow, edi88130lp Datasheet

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edi88130lp

Manufacturer Part Number
edi88130lp
Description
128kx8 Monolithic Sram, 5962-89598
Manufacturer
ETC-unknow
Datasheet

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128KX8 MONOLITHIC SRAM, SMD 5962-89598
FEATURES
n Access Times of 70, 85, 100ns
n Available with Single Chip Selects (EDI88128) or Dual
n 2V Data Retention (LP Versions)
n CS and OE Functions for Bus Control
n TTL Compatible Inputs and Outputs
n Fully Static, No Clocks
n Organized as 128Kx8
n Industrial, Military and Commercial Temperature Ranges
n Thru-hole and Surface Mount Packages JEDEC Pinout
n Single +5V (±10%) Supply Operation
March 2002 Rev. 16
* Pin 30 is NC for 88128 or CS2 for 88130.
F
Chip Selects (EDI88130)
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)
• 32 lead Ceramic SOJ (Package 140)
IG
. 1
I/OØ
I/O1
I/O2
A16
A14
A12
V
NC
A7
A6
A5
A4
A3
A2
A1
SS
P C
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
T
32 DIP
32 SOJ
V
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
A15
NC/CS2*
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
CC
1
The EDI88128C is a high speed, high performance, Mono-
lithic CMOS Static RAM organized as 128Kx8.
The device is also available as EDI88130C with an additional
chip select line (CS2) which will automatically power down
the device when proper logic levels are applied.
The second chip select line (CS2) can be used to provide
system memory security during power down in non-battery
backed up systems and simplifiy decoding schemes in memory
banking where large multiple pages of memory are required.
The EDI88128C and the EDI88130C have eight bi-directional
input-output lines to provide simultaneous access to all
bits in a word. An automatic power down feature permits
the on-chip circuitry to enter a very low standby mode and
be brought back into operation at a speed equal to the
address access time.
Low power versions, EDI88128LP and EDI88130LP, offer a
2V data retention function for battery back-up opperation.
Military product is available compliant to Appendix A of
MIL-PRF-38535.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
CS
I/O
A
V
WE
1
OE
V
NC
0-16
, CS
CC
SS
0-7
P D
B
2
Power (+5V ±10%)
Data Inputs/Outputs
Not Connected
Address Inputs
Output Enable
D
Write Enable
Chip Selects
Ground
EDI88128C

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edi88130lp Summary of contents

Page 1

... Low power versions, EDI88128LP and EDI88130LP, offer a 2V data retention function for battery back-up opperation. Military product is available compliant to Appendix A of MIL-PRF-38535 ...

Page 2

Voltage on any pin relative to Vss A Commercial Industrial Military Storage Temperature, Plastic Power Dissipation Output Current Junction Temperature NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to ...

Page 3

CC = 5.0V 0V -55°C Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold ...

Page 4

CC = 5.0V 0V -55°C Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write ...

Page 5

AVAV ADDRESS ADDRESS 1 ADDRESS AVQV AVQX DATA I/O DATA 1 READ CYCLE 1 (WE HIGH; OE, CS LOW ADDRESS WE CS ...

Page 6

... Parameter guaranteed by design, but not tested. * Read Cycle Time CS1 C Vcc CS2 C Vcc CS 2 White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 C (EDI88128LP & EDI88130LP ONLY) (TA = -55°C +125° 2. ³ -0. ³ -0.2V CDR ...

Page 7

IDEBRAZED ERAMIC Pin 1 Indicator 0.200 0.125 0.061 0.017 P 140 SOJ EAD ERAMIC 0.840 0.820 D (600 ) IP MILS WIDE 1.616 1.584 0.060 0.040 0.155 0.115 0.020 0.100 ...

Page 8

130 = Dual Chip Select C = CMOS Standard Power LP = Low Power lead Sidebrazed DIP, 600 mil (Package lead Ceramic SOJ (Package 140 MIL-STD-883 Compliant M ...

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