atr0621

Manufacturer Part Numberatr0621
DescriptionGps Baseband Processor - Atmel Corporation
ManufacturerATMEL Corporation
atr0621 datasheet
 
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Features
16 Channel GPS Correlator
– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (Stand-Alone, S/A off)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –140 dBm
– Tracking Sensitivity: –150 dBm
®
®
Utilizes the ARM7TDMI
ARM
Thumb
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Embedded ICE (In-circuit Emulator)
128 Kbyte Internal RAM
384 Kbyte Internal ROM with u-blox GPS Firmware
Fully Programmable External Bus Interface (EBI)
– Maximum External Address Space of 8 Mbytes
– Up to 4 Chip Selects
– Software Programmable 8-bit/16-bit External Data Bus
6-channel Peripheral Data Controller (PDC)
8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 2 External Interrupts
32 User-programmable I/O Lines
1 USB Device Port
– Universal Serial Bus (USB) V2.0 Full-speed Device Specification Compliant
– Embedded USB V2.0 Full-speed Transceiver
– Suspend/Resume Logic
– Ping-pong Mode for Isochronous and Bulk Endpoints
2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
Master/Slave SPI Interface
– 2 Dedicated Peripheral Data Controller (PDC) Channels
– 8-bit to 16-bit Programmable Data Length
– 4 External Slave Chip Selects
Programmable Watchdog Timer
Advanced Power Management Controller (APMC)
– Peripherals Can Be Deactivated Individually
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
Real Time Clock (RTC)
2.3V to 3.6V or 1.8V Supply Voltage
Includes Power Supervisor
1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance
1 Kbyte Battery Backup Memory
9 mm × 9 mm 100-pin BGA Package (LFBGA100)
Electrostatic sensitive device.
Observe precautions for handling.
®
Processor Core
Note: This is a summary document. A complete document
is available under NDA. For more information, please con-
tact your local Atmel sales office.
GPS Baseband
Processor
ATR0621
Summary
Preliminary
Rev. 4890AS–GPS–09/05

atr0621 Summary of contents

  • Page 1

    ... Electrostatic sensitive device. Observe precautions for handling. ® Processor Core Note: This is a summary document. A complete document is available under NDA. For more information, please con- tact your local Atmel sales office. GPS Baseband Processor ATR0621 Summary Preliminary Rev. 4890AS–GPS–09/05 ...

  • Page 2

    ... The ATR0621 is manufactured using the Atmel high-density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator and a wide range of peripheral functions on a monolithic chip, the ATR0621 provides a highly-flexi- ble and cost-effective solution for GPS applications. ATR0621 [Preliminary] 2 ® ...

  • Page 3

    ... P30/AGCOUT0 P8/STATUSLED P16/NEEPROM P11/EM_A21 P28/EM_A20 P10/EM_A0/NLB P7/NUB/NWR1 P6/NOE/NRD P5/NWE/NWR0 P4/nCS0 P3/nCS1 EM_A19 EM_A1 EM_DA15 EM_DA0 DBG_EN NTRST TDI TDO TCK TMS NRESET 4890AS–GPS–09/05 ATR0621 [Preliminary] SIGLO0 SIGHI0 P21/TXD2 P22/RXD2 P18/TXD1 P31/RXD1 USB_DP USB_DM VBAT18 VBAT LDOBAT_IN LDO_OUT LDO_IN LDO_EN 3 ...

  • Page 4

    ... Architectural Overview 2.1 Description The ATR0621 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter- faces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI) ...

  • Page 5

    ... Pin Configuration 3.1 Pinout Figure 3-1. Pinout LFBGA100 (Top View) Table 3-1. ATR0621 Pinout Pin Name LFBGA100 Pin Type CLK23 G9 IN DBG_EN H4 IN EM_A1 A6 OUT EM_A2 A5 OUT EM_A3 A4 OUT EM_A4 A2 OUT EM_A5 A3 OUT EM_A6 B5 OUT EM_A7 B4 OUT EM_A8 B2 OUT EM_A9 D4 OUT EM_A10 C2 OUT EM_A11 ...

  • Page 6

    ... Table 3-1. ATR0621 Pinout (Continued) Pin Name LFBGA100 Pin Type EM_A18 B3 OUT EM_A19 C5 OUT EM_DA0 B6 I/O EM_DA1 B10 I/O EM_DA2 C7 I/O EM_DA3 C10 I/O EM_DA4 D10 I/O EM_DA5 E7 I/O EM_DA6 E9 I/O EM_DA7 B7 I/O EM_DA8 B8 I/O EM_DA9 A9 I/O EM_DA10 C8 I/O EM_DA11 B9 I/O EM_DA12 D8 I/O EM_DA13 C9 I/O EM_DA14 D9 I/O EM_DA15 E8 I/O GND A1 IN GND A10 IN GND K1 IN GND K10 IN LDOBAT_IN ...

  • Page 7

    ... Table 3-1. ATR0621 Pinout (Continued) Pin Name LFBGA100 Pin Type I/O P10 E4 I/O P11 H10 I/O P12 F3 I/O P13 G10 I/O P14 J5 I/O P15 K5 I/O P16 E1 I/O P17 J4 I/O P18 K4 I/O P19 F1 I/O P20 H2 I/O P21 F2 I/O P22 H8 I/O P23 H3 I/O P24 H1 I/O P25 D1 I/O P26 G8 I/O P27 E2 I/O P28 G1 I/O P29 E3 I/O P30 G5 I/O P31 H9 I/O RF_ON K6 OUT SIGHI0 F9 OUT ...

  • Page 8

    ... Table 3-1. ATR0621 Pinout (Continued) Pin Name LFBGA100 Pin Type VBAT18 G6 OUT VDD18 E6 IN VDD18 F7 IN VDD18 F6 IN (2) VDDIO E5 IN (3) VDD_USB F5 IN XT_IN J9 IN XT_OUT J10 OUT Notes internal pull-down resistor internal pull-up resistor switched to Output High at reset 2. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 3 ...

  • Page 9

    ... Table 3-2. ATR0621 Signal Description (Continued) Module Name Function SCK SPI Clock MOSI Master Out Slave In SPI MISO Master In Slave Out NSS/NPCS0 Slave Select NPCS1-3 Slave Select WD NWD_OVF Watchdog Timer Overflow PIO P0-31 Programmable I/O Port GPSMODE0-12 GPS Mode SIGHI1 Digital IF SIGLO1 Digital IF GPS ...

  • Page 10

    ... Table 3-5. GPSMODE3 (Fixed PU ATR0621 [Preliminary] 10 GPSMODE Functions Function Enable configuration with GPSMODE pins This pin is used for FixNow functionality and not used for GPSMODE configuration GPS sensitivity settings This pin (NAADET1) is used as active antenna supervisor input and not used for ...

  • Page 11

    ... Serial I/O Configuration The ATR0621 features a two-stage I/O message and protocol selection procedure for the two available serial ports. At the first stage, a certain protocol can be enabled or disabled for a given USART port. Selectable protocols are RTCM, NMEA and UBX. At the second stage, messages can be enabled or disabled for each enabled protocol on each port. In all configura- tions discussed below, all protocols are enabled on all ports ...

  • Page 12

    ... USB host; that is, the device classifies itself as a “low-power bus-powered function” with no more than one USB power unit load. Table 3-12. GPSMODE7 (Reset = PU) Description ATR0621 [Preliminary] 12 Supported Messages at Setting High Standard GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST ...

  • Page 13

    ... P25/NAADET0/MISO 1 0 P14/NAADET1 1 1 P14/NAADET1 (Default P14/NAADET1 0 1 P14/NAADET1 1 0 P25/NAADET0/MISO 1 1 P25/NAADET0/MISO ATR0621 [Preliminary] Comment Reserved for further use. Do not use this setting. Reserved for further use. Do not use this setting. Reserved for further use. Do not use this setting. 13 ...

  • Page 14

    ... Enable Open Circuit Detection via NAADET 3.4 External Connections for a Working GPS System Figure 3-2. Example of an External Connection ATR0601 SIGH SIGL +3V (see Power Supply) (see Power Supply) ATR0621 [Preliminary] 14 ATR0621 SIGHI SIGLO CLK23 RF_ON NSLEEP NC NRESET See Table 3-15 EM_DA0 - 15 NC EM_A1 - 19 ...

  • Page 15

    ... Note: “Never leave open” means: This pin needs a defined level, even if VDD18 is not supplied and system is in backup mode. 4890AS–GPS–09/05 ATR0621 [Preliminary] 10. Can be left open if configured as output by user application. If 10. Can be left open if not used as GPSMODE pin and 10 ...

  • Page 16

    ... Note: “Never leave open” means: This pin needs a defined level, even if VDD18 is not supplied and system is in backup mode. ATR0621 [Preliminary] 16 10. Can be left open if not used as GPSMODE pin and 10 ...

  • Page 17

    ... VBAT EM_DA0 to EM_DA15, P0 P7, P10, P11, P15, P28, P30, SIGHI, SIGLO, CLK23, XT_IN, TMS, TCK, TDI, NTRST, DBG_EN, LDO_EN, NRESET USB_DM, USB_DP P1, P2, P8, P9, P12 to P14, P16 to P27, P29, P30 ATR0621 internal RTC Min. Max. Unit –40 +85 °C –60 +150 ° ...

  • Page 18

    ... VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 2. Values defined for operating the USB interface. Otherwise VDD_USB may be connected to 1. supply. 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT. ATR0621 [Preliminary] 18 Pin Symbol Min ...

  • Page 19

    ... technical drawings according to DIN specifications Drawing-No.: 6.580-5003.01-4 Issue: 1; 02.09.05 4890AS–GPS–09/05 ATR0621 [Preliminary] Package LFBGA100 9 mm × 9 mm, 0.80 mm pitch, Pb-free ∅ 0. ∅ 0.15 M Bottom View 7.2 0.15 (4x ±0. ...

  • Page 20

    ... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2005. All rights reserved. Atmel trademarks or trademarks of Atmel Corporation or its subsidiaries. ARM product names may be trademarks of others. Atmel Operations ...