mc5474hc161a ETC-unknow, mc5474hc161a Datasheet - Page 5

• Manufacturer Part Number: mc5474hc161a
• Description: Presettable Counters
• Manufacturer: ETC-unknow

High–Speed CMOS Logic Data
DL129 — Rev 6
counters that feature parallel Load, synchronous or asynch-
ronous Reset, a Carry Output for cascading and count–
enable controls.
asynchronous Reset and synchronous Reset, respectively.
INPUTS
Clock (Pin 2)
vances with the rising edge of the Clock input. In addition,
control functions, such as resetting and loading occur with
the rising edge of the Clock input.
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
Data on these pins may be synchronously loaded into the in-
ternal flip–flops and appear at the counter outputs. P0 (Pin 3)
is the least–significant bit and P3 (Pin 6) is the most–signifi-
cant bit.
OUTPUTS
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
significant bit and Q3 (Pin 11) is the most–significant bit.
Ripple Carry Out (Pin 15)
goes high, providing an external look–ahead carry pulse that
may be used to enable successive cascaded counters. Rip-
ple Carry Out remains high only during the maximum count
state. The logic equation for this output is:
The HC161A/163A are programmable 4–bit synchronous
The HC161A and HC163A are binary counters with
The internal flip–flops toggle and the output count ad-
These are the data inputs for programmable counting.
These are the counter outputs. Q0 (Pin 14) is the least–
When the counter is in its maximum state 1111, this output
Ripple Carry Out = Enable T Q0 Q1 Q2 Q3
15
14
13
12
0
OUTPUT STATE DIAGRAMS
FUNCTION DESCRIPTION
11
1
Binary Counters
3–5
10
2
CONTROL FUNCTIONS
Resetting
flops and sets the outputs (Q0 through Q3) to a low level.
The HC161A resets asynchronously, and the HC163A resets
with the rising edge of the Clock input (synchronous reset).
Loading
9) loads the data from the Preset Data input pins (P0, P1, P2,
P3) into the internal flip–flops and onto the output pins, Q0
through Q3. The count function is disabled as long as Load is
low.
Count Enable/Disable
able P (Pin 7) and Enable T (Pin 10). The devices count
when these two pins and the Load pin are high. The logic
equation is:
puts according to Table 1. In general, Enable P is a count–
enable control: Enable T is both a count–enable and a
Ripple–Carry Output control.
* Q0 through Q3 are maximum when Q3 Q2 Q1 Q0 = 1111.
Load
A low level on the Reset pin (Pin 1) resets the internal flip–
With the rising edge of the Clock, a low level on Load (Pin
These devices have two count–enable control pins: En-
The count is either enabled or disabled by the control in-
H
L
X
X
3
9
Count Enable = Enable P Enable T Load
Control Inputs
Enable P
H
H
X
MC54/74HC161A MC54/74HC163A
L
Table 1. Count Enable/Disable
4
5
6
7
8
Enable T
H
H
H
L
No Count
No Count
No Count
Q0 – Q3
Count
Result at Outputs
High when Q0–Q3
High when Q0–Q3
are maximum*
are maximum*
High when Q0–Q3
are maximum*
Ripple Carry Out
MOTOROLA
L