ncs36000 ON Semiconductor, ncs36000 Datasheet - Page 5

• Manufacturer Part Number: ncs36000
• Description: Ncs36000 Product Preview Passive Infrared Pir Detector Controller
• Manufacturer: ON Semiconductor

Digital Signal Processing Block (all times assume a
62.5 Hz system oscillator frequency)
major functions.
start−up sequencing at approximately two hertz regardless
of the state of the XLED_EN pin. The startup sequence lasts
for thirty seconds. During that time the OUT pin is held low
regardless of the state of OP2_O.
is to insure a certain glitch width is seen before OUT is
toggled. The digital signal processing block is synchronous
with the system oscillator frequency and therefore the
deglitch time is related to when the comparators toggle
within the oscillator period. A signal width less than two
clock period is guaranteed to be deglitched as a zero. A
signal width of greater than three clock cycles is guaranteed
to be de−glitched. It should be noted that down−sampling
can occur if sufficient anti−aliasing is not performed at the
input of the circuit (OPI_P) or if noise is injected into the
amplifiers, an example would be a noisy power supply.
The digital signaling processing block performs three
The first function is that the device toggles LED during the
The second function of the digital signal processing block
Sensor dependent
components
D
G
COMP_N
COMP_P
OP2_O
MODE
VREF
Figure 5. Figure Showing Simplified Block Diagram of Analog Conditioning Stages
OSC
OUT
LED
6
1
2
Ï Ï Ï Ï Ï Ï
Ï Ï Ï Ï Ï Ï
Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï
Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï Ï
+
−
Start− up Sequencing
Figure 6. Timing Diagram for Single−Pulse Mode Detection
LDO
Application dependent
components
3
Vm
<32m Sec
http://onsemi.com
5
+
−
>48m Sec
5
to recognize different pulse signatures coming from the
window comparator block. The device is equipped with two
pulse recognition routines. Single pulse mode (MODE tied
to VSS) will trigger the OUT pin if either comparator toggles
and the deglitch time is of the appropriate length. (See
Figure 6). Dual pulse mode (MODE tied to V
two pulses with each pulse coming from the opposite
comparator to occur within a timeout window of five
seconds (See Figure 7). If the adjacent pulses occur outside
the timeout window then the digital processing block will
restart the pulse recognition routine (Figure 8).
xLED_EN Pin
motion has been detected. If xLED_EN is tied high the LED
pin will not toggle after motion is detected. If the xLED_EN
is tied low the LED pin will toggle when motion is detected.
During start-up the LED pin will toggle irrespective of how
the xLED_EN pin is tied. (See Figure 6).
The third function of the digital signal processing block is
The xLED_EN pin enables the LED output driver when
4
If xLED_EN = 0
OP2_O
~1.6 Sec
Vh
Vl
>48m Sec
+
+
Comp_N
−
Comp_P
−
If xLED_EN = 0
~1.6 Sec
VREF 6
DD
) requires
Vm
Vh
Vl