la6543 Sanyo Semiconductor Corporation, la6543 Datasheet - Page 7

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la6543

Manufacturer Part Number
la6543
Description
4-channel Bridge Btl Driver For Cd-rom
Manufacturer
Sanyo Semiconductor Corporation
Datasheet

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Gain Setting (input pins and adjustment pins)
Offset Voltage
(V
A simplified diagram of V
1) Consider an 11 k
2) When not the pin VG but the pin V
3) Gain is set by the input impedance as seen from point A.
This IC incorporates a level shifter circuit. The input references the voltage V
SS
When VG only is used and the external resistor is R, the BTL gain (between V
20 log (11 k
When an 11 k
Rz = 5.5 k . Gain is
CH1 to CH3 : 20 log (11 k /5.5 k ) + 7 dB = 13 dB
CH4
for AMP only). For CH4, it is 14 dB (8 dB for AMP only). This also applies for the case when V
external resistor is connected to VG for input.
1)/2V for channels 1 to 3 or the voltage (V
This catalog provides information as of December, 1998. Specifications and information herein are subject to change
without notice.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products(including technical data,services) described or
contained herein are controlled under any of applicable local export control laws and regulations,
such products must not be exported without obtaining the export license from the authorities
concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co. , Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
: 20 log (11 k /5.5 k ) + 14 dB = 20 dB.
/R) + 14 dB.
resistor is inserted between V
(typ.) resistor inserted between V
IN
V REF
and VG is shown below.
V SS
VG
V IN
11 k
11 k
GND
IN
is used alone, the BTL gain (between V
+
+
CH4 only
V REF 1
V REF 2
11 k
SS
IN
2–V
and VG, and input is via V
BE
IN
(0.7))/2V for channel 4 to be output.
and VG.
LA6543
A
Level
shift
IN
, the combined resistance Rz as seen from point A is
REF
O
+
O
and V
to be applied and references the voltage
+
and V
O
O
+
+
) is set to 7 dB for CH1 to CH3 (1 dB
AMP1
AMP2
)
is
IN
is not used and an 11 k
A11150
V O
V O
+
PS
No. 5973-7/7

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