dac-hk C&D Technologies., dac-hk Datasheet - Page 2

• Manufacturer Part Number: dac-hk
• Description: High-performance, 12-bit Dac?s With Input Registers
• Manufacturer: C&D Technologies.

ABSOLUTE MAXIMUM RATINGS
DAC-HK Series
FUNCTIONAL SPECIFICATIONS
(Typical at +25°C and ±15V and +5V supplies unless otherwise noted.)
PHYSICAL ENVIRONMENTAL
Positive Supply, Pin 22
Negative Supply, Pin 14
Logic Supply, Pin 13
Digital Input Voltage, Pins 1–12 & 16
Output Current, Pin 15
Lead Temperature (soldering, 10s)
INPUTS
Resolution
Coding, Unipolar Output
Coding, Bipolar Output
Input Logic Level, Bit ON ("1")
Input Logic Level, Bit OFF ("0")
Logic Loading
Load Input
Load Input Loading
PERFORMANCE
Nonlinearity Error, max.
Differential Nonlinearity Error, max.
Gain Error, Before Trimming
Zero Error, Before Trimming
Gain Tempco, max.
Zero Tempco, Unipolar, max.
Offset Tempco, Bipolar, max.
Diff. Nonlinearity Tempco, max.
Monotonicity
Settling Time, 5V Change
Settling Time, 10V Change
Settling Time, 20V Change
Settling Time, 1LSB Change
Slew Rate
Power Supply Rejection
OUTPUTS
Output Voltage Ranges, Unipolar
Output Voltage Ranges, Bipolar
Output Current
Output Impedance
POWER REQUIREMENTS
Power Supply Voltages
Operating Temperature Range, Case
Storage Temperature Range
Package Type
Weight
Footnotes:
For two’s complement coding, order the "-2" model as described
in Ordering Information.
Logic levels are the same as for data inputs.
Initial errors are trimmable to zero. See Connection Diagram.
FSR is full scale range and is 10V for 0 to +10V output range,
20V for ±10V output range, etc.
By external pin connection.
For ±12V, +5V operation, contact factory.
DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048-1194 (U.S.A.) Tel: [phone] Fax: [phone] • For immediate assistance 800-233-2765
12 bits
Straight binary
Offset binary, two’s complement
+2.0V to +5.5V
0V to +0.8V
1 LSTTL load
High (“1”) = hold data
Low (“0”) = transfer data
3 LSTTL loads
±1/2LSB
±3/4LSB
±0.1%
±0.1% of FSR
±20ppm/°C
±5ppm/°C of FSR
±10ppm/°C of FSR
±2ppm/°C of FSR
Guaranteed over temperature
3 s
3 s
4 s
800ns
±20V/ s
±0.002%FSR/%
0 to +5V, 0 to +10V
±2.5V
±5V
±10V
±5mA min.
0.05 Ohm
+15V, ±0.5V at 15mA
–15V, ±0.5V at 30mA
+5V, ±0.25V at 65mA
0°C to +70°C (BGC, BMC)
–55°C to +125°C (BMM, 883)
–65°C to +125°C
24-pin DDIP
0.22 ounces (6.3 grams)
+18V
–18V
+5.25V
+5.5V
±20mA
300°C
TECHNICAL NOTES
1. It is recommended that these converters be operated with
2. The analog, digital and power grounds should be separated
3. The “load” control pin is a level-triggered input which causes
4. A setup time of 50ns minimum must be allowed for the input
5. If the reference output terminal (pin 24) is used, an
CALIBRATION PROCEDURE
Select the desired output voltage range and connect the
converter as shown in the Output Range Selection Table and
the Connection Diagrams. Refer to the Coding Tables.
Unipolar Operation
1. Zero Adjustment. Set the input digital code to 0000 0000
2. Gain Adjustment. Set the input digital code to 1111 1111
Bipolar Operation
1. Offset Adjustment. Set the digital input code to 0000 0000
2. Gain Adjustment. Set the digital input code to 1111 1111
OUTPUT TO
ALL RISE AND FALL TIMES
local supply bypass capacitors of 1 F (tantalum type) at the
+15V, –15V and +5V supply pins. The capacitors should be
connected as close to the pins as possible. In high RFI
noise environments, these capacitors should be shunted
with 0.01 F ceramic capacitors.
from each other as close as possible to pin 21 where they
all must come together.
the register to hold data with a high input and transfer data
to the DAC with a low input.
data. The DAC output voltage begins to change when the
register output changes.
operational amplifier in non-inverting mode should be used
as a buffer. Current drawn from pin 24 should be limited to
±10 A in order not to affect the T.C. of the reference
0000 and adjust the ZERO ADJ. potentiometer to give
0.0000V output.
1111 (straight binary) and adjust the GAIN ADJ. potentiom-
eter to give the full-scale output voltage shown in Table 1.
0000 (offset binary) or 1000 0000 0000 (two’s complement)
and adjust the OFFSET ADJ. potentiometer to give the
negative full-scale output voltage shown in Table 2.
1111 (offset binary) or 0111 1111 1111 (two’s complement)
and adjust the GAIN ADJ. potentiometer to give the positive
full-scale output voltage shown in Table 2.
REGISTER
DATA IN
LOAD
DAC
0
1
Hold
Transfer
50nsec min.
Figure 2. DAC-HK Timing
t
SETUP
60nsec
t
10nsec
PHL
50nsec min.
t
®
SETUP
60nsec
t
PLH
®