s4806cbi ETC-unknow, s4806cbi Datasheet - Page 3

• Manufacturer Part Number: s4806cbi
• Description: Sts-48/stm-16 Sonet/sdh Framer Atm/pos Mapper
• Manufacturer: ETC-unknow

DS3 Processing
The S4806 can be configured to support DS3 mapping/demap-
ping of ATM, HDLC or directly-mapped payloads on a per tribu-
tary basis. The S4806 supports the C-bit parity and M23 DS3
frame formats.
DS3 frame generation (Transmit)
In the Transmit direction, the S4806 maps the data received
from the ATM or HDLC processor into the payload of a DS3
frame. It also generates DS3 Overhead bits and, for channels
operating in C-bit mode, inserts the Terminal to Terminal Data
Link information. Additionally, the OHIO can be provisionned to
generate IDLE or AIS signals on any active DS3 channel. The
DS3 frames are subsequently mapped into SONET STS-1 SPE
or in SDH VC3 Virtual Container.
DS3 framing and demapping (Receive)
In the RX direction, the S4806 frames the DS3 signals and
monitors the signal for Errors, Alarms or Idle conditions detec-
tion. In C-bit mode, it extracts the Data Link channels and
makes it available to the user through an external interface. The
data payload is demapped and passed through the ATM, HDLC
or Direct Map Mode processors.
For testing purposes, the S4806 includes a Pseudo Random Bit
Sequence generator (Tx) and monitor (Rx) and any one DS3
can be replaced by a PRBS sequence.
TDM/Circuit Drops
In addition to the FlexBus
provides a single telecom-type interface to allow for add/drop of
TDM tributaries. This TDM interface can operate as either a 4-
bit wide STS-48/STM-16 signal, or as 4xSTS-12/STM-4
SONET/SDH signals, both operating at 622.08 MHz. The signal
format adheres to the SONET/SDH frame structure, with valid
A1A2, B1 and H1H2H3 pointer bytes.
For backplane applications, the TDM port’s High Speed Serial
Link mode provides clock recovery for the 622MHz signals as
long as a low speed (78MHz) reference clock that is frequency
synchronous to the data stream is supplied to the device.
The TDM port can interface directly to the AMCC S1204
Orinoco device, or the S2509. The S1204 Orinoco will interface
with the STS-12/STM-4 TDM ports of the S4806, and provide
insertion/extraction of DS3, E3 or clear channel STS-1/STM-0
tributaries to/from these TDM add/drop signals. The S2509 pro-
vides the capability to serialize a 4-bit wide STS-48 signal into a
single 2.5 Gb/s serial backplane signal.
Redundancy Features
The 4x622 Mb/s TDM ports can also be used as APS input and
output interfaces to convey signals between two S4806 devices
configured for APS operation. This configuration supports 1+1
and 1:1 protection in linear, UPSR and BLSR configurations.
The TDM interface provides fully compliant SONET/SDH trans-
mit and receive TOH monitoring/generation for both 4-bit wide
STS-48/STM-16 and 4xSTS-12/STM-4 modes of operation.
This enables the use of the TDM port as a redundant line inter-
face, allowing a single OHIO device to support linear 1+1 and
1:1 protection.
S4806CBI: OHIO
STS-48/STM-16 SONET/SDH Framer and ATM/POS Mapper
200 Minuteman Park, Andover, MA 01810 Ph: 978/623-0009 Fax:[phone]
TM
system interface, the S4806 also
AMCC - Confidential and Proprietary
Cross-Connect
The S4806 provides integrated cross-connection functionality,
to support all types of ring configurations, including hairpinning,
drop-add, drop-and-continue, and broadcast/multicast. A
144x48 STS-1 level cross-connect is placed in the transmit
direction of the S4806. The inputs to the cross-connect block
come from the 48 transmit ATM/HDLC processing blocks, the
receive data path, and the input TDM/APS port.
Additionally, the S4806 provides a 144x48 STS-1 level cross-
connect capability in front of the TDM/APS output port, to allow
for grooming of the TDM/APS interface signals. The inputs to
this cross-connect come from the receive data path, the receive
TDM port and the SPE / VC generator.
Line-side Interface
For STS-48/STM-16 operation, the S4806 supports a 4-bit par-
allel line-side interface which operates at 622.08 MHz. In this
mode, the device is connected to the S3455 mux/demux and
clock recovery device. (See figure below.) For STS-12/STM-4
operation, the S4806 supports four serial line interfaces which
operate at 622.08 MHz. In this application, the device is con-
nected to four S3024 clock recovery devices.
System Interface
The S4806 provides a FlexBus-3
the transfer of ATM cells or packet data between the S4806 and
a link layer device. For ATM cell transfer, the Flexbus-3
face operates as a 100 MHz 32 bit UTOPIA Level 3 interface.
The S4806 supports multi-PHY operation for up to 48 tributar-
ies. It also provides multiple TX/RX_CLAV signals for multi-
plexed polling operation.
For packet/direct data transfer, the FlexBus-3
extends the UTOPIA framework to accomodate the variable
length nature of packet traffic. In this mode, the S4806 also sup-
ports multi-PHY operation for up to 48 tributaries with multiple
TX/RX_PA signals for multiplexed polling operation. Alterna-
tively, it can be configured to operate in SPI-3 mode as defined
by the Optical Internetworking Forum (OIF). The Flexbus-3
interface also has extensions to support Direct Map Mode oper-
ation.
Microprocessor Interface
The user of the S4806 can select between an 8-bit asynchro-
nous or a 16-bit synchronous microprocessor interface for
device control and monitoring. The interface supports both Intel
and Motorola type microprocessors, and is capable of operating
in either an interrupt driven or polled-mode configurations.
ADVANCED PRODUCT BRIEF
Product Brief Version 1.3 - April 2001
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system interface to allow
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