89ttm552 Integrated Device Technology, 89ttm552 Datasheet - Page 7

• Manufacturer Part Number: 89ttm552
• Description: Standalone 10g Simplex Traffic Manager
• Manufacturer: Integrated Device Technology

IDT 89TTM552
LLST_CLK_CP (C),
LLST_CLK_CN (C#)
LLST_CLK_KP (K),
LLST_CLK_KN (K#)
LLST_ADDR[21:0]
LLST_RD_N
LLST_WR_N
LLST_DIN[17:0]
LLST_DOUT[17:0]
LLST_VREF[1:0]
MC_CLK_CP (C),
MC_CLK_CN (C#)
MC_CLK_KP (K),
MC_CLK_KN (K#)
MC_ADDR[21:0]
MC_RD_N
MC_WR_N
MC_DIN[17:0]
Signal Name
Signal Name
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
I/O Type
I/O Type
0.75V
Table 5 Multicast / Parent-Child QDR SRAM (Part 1 of 2)
Table 4 Linked-List QDR SRAM
Dir.
Dir.
—
O
O
O
O
O
O
O
O
O
I
I
I
I
7 of 37
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
Freq.
Freq.
—
LL QDR SRAM input clock: This clock pair registers data
inputs on the rising edge of C and C#. All synchronous inputs
must meet setup and hold times around the clock rising
edges.
LL QDR SRAM output clock: This clock pair times the address
and control outputs to the rising edge of K, and times the data
outputs on the rising edge of K and K#.
LL QDR SRAM address outputs:
LL QDR SRAM synchronous read output (active low): When
asserted, a read cycle is initiated to the external QDR SRAM
devices.
LL QDR SRAM synchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
LL QDR SRAM data inputs: Input data must meet setup and
hold times around the rising edges of C and C# during read
operations
LL QDR SRAM data outputs: Output data is synchronized to
the K and K# during write operations
HSTL reference. Nominally V
MC QDR SRAM input clock: This clock pair registers data
inputs on the rising edge of C and C#. All synchronous inputs
must meet setup and hold times around the clock rising
edges.
MC QDR SRAM output clock: This clock pair times the
address and control outputs to the rising edge of K, and times
the data outputs on the rising edge of K and K#.
MC QDR SRAM address outputs:
MC QDR SRAM synchronous read output (active low): When
asserted, a read cycle is initiated to the external QDR SRAM
devices.
MC QDR SRAM synchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
MC QDR SRAM data inputs: Input data must meet setup and
hold times around the rising edges of C and C# during read
operations
Remarks
Remarks
DDQ
/ 2, so connect to 0.75 V
April 7, 2005