lc89051v Sanyo Semiconductor Corporation, lc89051v Datasheet
lc89051v
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lc89051v Summary of contents
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... Ordering number : EN*5543 Preliminary Overview The LC89051V is for use in IEC958 format data transmission between digital audio equipment. This LSI is used on the receiving side, and handles synchronization with the input signal and demodulation of that signal to a normal format signal. Features • On-chip PLL circuit synchronizes with the transmitted IEC958 format signal. • ...
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... Microcontroller interface subcode Q and ID synchronization output 19 CKOUT O VCO clock output (free running, 384fs, or 512fs) 20 FS128 O 128fs clock output 21 BCK O Bit clock output 22 LRCK O L/R clock output (left channel = high, right channel = low) 23 DATAOUT O Audio data output 24 ERROR O PLL lock error mute output LC89051V Description No. 5543-2/15 ...
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... Block Diagram LC89051V Microcontroller interface No. 5543-3/15 ...
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... Note: 6. Applies to the CKSEL, AVOCK, TEST1, and TEST2 pins. CMOS levels. 7. Applies to the XMODE, SCLK/CL, XLAT/CE, SWDT/DI pins. CMOS Schmitt inputs. 8. Applies to the DIN2 pin. TTL Schmitt levels 3 25°C, input data kHz DD 10. Measured before the DIN1 pin input capacitor. LC89051V Symbol Conditions ...
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... WBO Output data setup time t DSO Output data hold time t DHO Output delay t BD Note: 13.Ta = 25° 5.0 V, with the circuit constants for 2 speed operation in the sample application circuit. DD LC89051V = 3 Conditions min 10 160 80 80 –10 = 4 Conditions min 10 80 ...
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... CL delay time delay time 44.1 kHz LD pulse width 88.2 kHz Data delay time Data delay time Input mode Output mode LC89051V Conditions min 100 100 50 50 1.0 50 typ max Unit µs ns 100 ns 136 µ ...
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... DQSY pulse width 88.2 kHz XLAT pulse width t WLA Data delay time Data delay time Input mode Output mode LC89051V Conditions min 100 100 50 50 100 100 typ max Unit µs 136 µ ...
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... The CKOUT clock output is set by the CKSEL pin as listed in the table below. CKSEL CKOUT L 384fs clock output H 512fs clock output The microcontroller interface format is also set by CKSEL as listed in the table below. CKSEL Microcontroller interface L Figure 2 H Figure 3 LC89051V PLL Loop Filter Structure No. 5543-8/15 ...
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... LC89051V Figure 1 Data Output Timing No. 5543-9/15 ...
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... LC89051V Figure 2 Microcontroller Interface Timing 1 No. 5543-10/15 ...
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... LC89051V Figure 3 Microcontroller Interface Timing 2 No. 5543-11/15 ...
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... DI5 and DI6: Set the audio data output format. DI5 L DI6 L 16-bit right- 20-bit right- DATAOUT justified justified MSB first LSB first All bits are set low immediately after XMODE is switched from low to high. DI0 and DI7 are not used. LC89051V ...
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... Flags + 80 data bits all H Detected ID Start ID • Output pins The output scheme used for SRDT/DO differs depending on the microcontroller interface format selected by CKSEL Format L Figure 2 H Figure 3 LC89051V ) or a shortening the start all L Shortening ID SRDT/DO High open-drain output ...
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... Normal system operation is started by setting XMODE high after the power supply has risen above at least 4.5 V (3.0 V). After power is applied, the system will be reset if a low level is applied once more to the XMODE pin. If XMODE is set low, the VCO free-running oscillator clock is output from CKOUT. LC89051V DATAOUT C bit ...
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... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. LC89051V 3.3-V operation Standard speed ...