CS200L FUJITSU [Fujitsu Component Limited.], CS200L Datasheet

CS200L

Manufacturer Part Number

CS200L

Description

65nm CMOS Standard Cell

Manufacturer

FUJITSU [Fujitsu Component Limited.]

Datasheet

1.CS200L.pdf (2 pages)

Current page: 1 of 2
Download datasheet (984Kb)

65nm CMOS Standard Cell

CS200 ASIC Series

Features

Description

• High integration

• Low power consumption/low leakage current

• I/O with pad structure with fine pad pitch technology for chip

• High-speed library and low-power library available

• Higher performance, gate propagation delay tpd = 4.4ps

• Compiled memory macros: 1T and 6T SRAMs, and ROM

CS200 Series, 65nm standard cells CMOS process technology,

addresses the design challenges of the PDA and mobile computing

market in low power and multi-functionality. It also addresses

the need of ultra high performance design in leading-edge

– Transistor of 30–50nm gate length (ITRS road map 65nm)

– 12-layer fine pitch, copper wiring, and low-K insulating

– Maximum 180 million gates, nearly twice that of 90nm

– 50% reduction in SRAM cell size

– 30% increase in performance over 90nm

size reduction

– High speed: CS200HP

– Low leak: CS200L

(@1.2V, inverter, and F/O = 1, CS200HP)

material techniques

technology

Low Power

Cellular Phone

CS200LL

CS200A

Lineup

LL-Tr

STD-Tr

Digital Consumer

HS-Tr

Speed

Mobile

Computing

• Application specific IPs

• High-speed interface SerDes macros (~10Gbps data rate)

• Wide range of PLLs: standard to high-speed 1.6GHz

• Standard I/Os: LVTTL, SSTL, HSTL, LVDS, P-CML

• Wide supply voltage (0.80V to 1.30V for core)

• Triple Vth Transistor options

• Various packages available (QFP, FBGA, EBGA, PBGA,

• Design methodology and support

networking, server computing, and in complex telecom

equipment applications. 65nm technology is available in 300mm

fabrication and supports high volume wafer capacity in multiple

manufacturing locations.

UHS-Tr

– Computational cores: ARM7, 9, 11, Communication and

– Mixed signals: Wide range of ADCs and DACs

– HSIF logics: PCI-Express, XAUI, SATA, DDR, USB, HDMI

FC-BGA)

– Methodology in place to support multi-million-gates

– Excellent design center support at Sunnyvale and Dallas

– Worldwide service organizations for global support

UHS-Tr

Digital-AV DSP

hierarchical designs

Server/

Network

HV-Tr

UHS: Ultra High Speed, HS: High Speed

STD: Standard, LL: Low Leakage

D-

STD-Tr

D-

High Performance

Lineup CS200HP

Lineup CS200

Performance

HS-Tr

High

HS-Tr

D-

High End Server

Fast

Related parts for CS200L

CS200L Summary of contents

Page 1

... I/O with pad structure with fine pad pitch technology for chip size reduction • High-speed library and low-power library available – High speed: CS200HP – Low leak: CS200L • Higher performance, gate propagation delay tpd = 4.4ps (@1.2V, inverter, and F CS200HP) • Compiled memory macros: 1T and 6T SRAMs, and ROM ...

Page 2

CMOS Standard Cell 65nm compared to 90nm of the same design SRAM 6.3mm LOGIC Analog I/O Peripheral Specifications Memory Macros and Compilers • SRAM in 16K X 40-bit Max. Configuration • SRAM ...

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