FM25L256-G ETC [List of Unclassifed Manufacturers], FM25L256-G Datasheet
FM25L256-G
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FM25L256-G Summary of contents
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... SOIC and 8-pin DFN Packages “Green” Packaging Options Pin Configuration caused by VSS lower power Pin Name /CS /WP /HOLD SCK SI SO VDD VSS drop-in Ordering Information FM25L256-S FM25L256-G FM25L256-DG VDD 1 8 HOLD 2 7 SCK VDD / /HOLD SO SCK ...
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... SO may be connected to SI for a single pin data interface. VDD Supply Power Supply (2.7V to 3.6V) VSS Supply Ground Rev. 2.0 Apr. 2005 8192 x 32 FRAM Array 15 Data I/O Register Nonvolatile Status Register Figure 1. Block Diagram specifications. DD FM25L256 Page ...
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... This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25L256 due to its fast write cycle and high endurance as compared to EEPROM. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly ...
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... SPI Mode 3: CPOL=1, CPHA=1 7 Rev. 2.0 Apr. 2005 SO SI SCK SO SI SCK FM25L256 FM25L256 CS HOLD CS P1.0 P1 SCK FM25 L256 C S HOLD P1 Figure 4. SPI Modes 0 & 3 FM25L256 HOLD MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select Page ...
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... Power Up to First Access The FM25L256 is not accessible for a period of time (10 ms) after power up. Users must comply with the timing parameter t , which is the minimum time PU from V (min) to the first /CS low. DD Data Transfer All data transfers to and from the FM25L256 occur in 8-bit groups. They are synchronized to the clock signal (SCK), and they transfer most significant bit (MSB) first ...
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... Status register. Reading Status provides information about the current state of the write protection features. Following the RDSR op- code, the FM25L256 will return one byte with the contents of the Status register. The Status register is described in detail in a later section. ...
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... The SPI interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the FRAM technology. Unlike SPI-bus EEPROMs, the FM25L256 can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed. Write Operation All writes to the memory array begin with a WREN op-code ...
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... MSB LSB Figure 9. Memory Write 16-bit Address MSB LSB Figure 10. Memory Read FM25L256 Data MSB LSB Data Out ...
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... Std JESD22-A115-A) = 2.7V to 3.6V unless otherwise specified) DD Min Typ 2 0 -0.3 V – other inputs -0.3V FM25L256 Ratings -1.0V to +5.0V -1.0V to +5.0V and V < V +1. - 125 C 300 C 3kV 1kV 100V MSL-1 Max Units Notes 3 0.25 mA 1.2 6 ...
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... C to +85 C) Min Max 2.7V to 3.6V) DD min 3.3V) DD Min - - waveform FM25L256 V 3 +70 C) Min Max Units Notes 0 25 MHz ...
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... SCK tH tSU SI SO /Hold Timing CS SCK HOLD SO Power Cycle Timing Data Retention (V = 2.7V to 3.6V) DD Parameter Data Retention Rev. 2.0 Apr. 2005 tCL tF tR tOH tODV tHS tHH tHS tHZ Min Max Units 10 - Years FM25L256 tD tCSH tCH tOD tHH tLZ Notes Page ...
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... SOIC Package Marking Scheme Legend: XXXX= part number, P= package type LLLLLLL= lot code XXXXXXX-P RIC=Ramtron Int’l Corp, YY=year, WW=work week LLLLLLL RICYYWW Example: FM25L256, Standard SOIC package, Year 2004, Work Week 39 FM25L256-S A40003S RIC0439 Rev. 2.0 Apr. 2005 Recommended PCB Footprint 3.90 ...
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... RIC=Ramtron Int’l Corp, G=”green” DFN package XXXX=base part number RICG LLLL= lot code XXXX YY=year, WW=work week LLLL YYWW Example: “Green” DFN package, FM25L256, Lot 0003, Year 2004, Work Week 39 RICG 5L25 0003 0439 Rev. 2.0 Apr. 2005 Exposed metal pad. ...
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... Added Power Down timing parameter and changed DD diagram. Removed “preliminary” from DFN package drawing. Added note about powering down with /CS active (pg 3). Added ESD and package MSL ratings. Changed to Pre-Production status. FM25L256 spec limit. Changed Page ...