16C6N4 RENESAS [Renesas Technology Corp], 16C6N4 Datasheet - Page 72

• Manufacturer Part Number: 16C6N4
• Description: Renesas MCU
• Manufacturer: RENESAS [Renesas Technology Corp]

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ03B0003-0240
Under development
This document is under development and its contents are subject to change.
Figure 5.20 Timing Diagram (8)
Memory Expansion Mode and Microprocessor Mode
(For 3-wait setting, external area access and multiplexed bus selection)
Read timing
Measuring conditions :
Aug 25, 2006
Write timing
tcyc =
WR, WRL
WRH
(no multiplex)
ALE
(no multiplex)
ALE
BCLK
CSi
ADi
/DBi
RD
BCLK
CSi
ADi
/DBi
BHE
BHE
ADi
ADi
VCC = 5 V
Input timing voltage : V
Output timing voltage : V
f(BCLK)
1
t
25ns.max
d(BCLK-ALE)
(0.5 ✕ tcyc-25)ns.min
t
25ns.max
d(BCLK-ALE)
t
t
25ns.max
d(AD-ALE)
d(BCLK-AD)
t
25ns.max
t
(0.5 ✕ tcyc-25)ns.min
d(BCLK-AD)
d(AD-ALE)
t
25ns.max
page 72 of 88
d(BCLK-CS)
t
25ns.max
d(BCLK-CS)
Address
Address
tcyc
tcyc
t
-4ns.min
h(BCLK-ALE)
t
d(AD-RD)
t
-4ns.min
0ns.min
h(BCLK-ALE)
IL
OL
= 0.8 V, V
= 0.4 V, V
(0.5 ✕ tcyc-15)ns.min
t
h(ALE-AD)
t
t
25ns.max
t
25ns.max
d(AD-WR)
d(BCLK-WR)
t
d(BCLK-RD)
t
40ns.max
dZ(RD-AD)
0ns.min
8ns.max
d(BCLK-DB)
IH
OH
= 2.0 V
= 2.4 V
(2.5 ✕ tcyc-45)ns.max
t
ac3(RD-DB)
(2.5 ✕ tcyc-40)ns.min
Data output
t
d(DB-WR)
t
40ns.min
Data input
SU(DB-RD)
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-10)ns.min
t
h(RD-CS)
5. Electric Characteristics (Normal-ver.)
t
h(WR-CS)
t
t
(0.5 ✕ tcyc-10)ns.min
t
(0.5 ✕ tcyc-10)ns.min
(0.5 ✕ tcyc-10)ns.min
h(WR-AD)
h(WR-DB)
h(RD-AD)
t
0ns.min
t
0ns.min
h(BCLK-WR)
h(RD-DB)
t
0ns.min
h(BCLK-RD)
t
4ns.min
t
4ns.min
t
4ns.min
h(BCLK-CS)
h(BCLK-CS)
h(BCLK-AD)
t
4ns.min
t
4ns.min
h(BCLK-AD)
h(BCLK-DB)
VCC = 5 V