ACS8515REV2.1T SEMTECH [Semtech Corporation], ACS8515REV2.1T Datasheet

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ACS8515REV2.1T

Manufacturer Part Number
ACS8515REV2.1T
Description
Line Card Protection Switch for SONET or SDH Network Elements
Manufacturer
SEMTECH [Semtech Corporation]
Datasheet

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The ACS8515 is a highly integrated, single-chip
solution for ‘hit-less’ protection switching of SEC
clocks from Master and Slave SETS clockcards
in a SONET or SDH Network Element. The
ACS8515 has fast activity monitors on the in-
puts and will implement automatic system pro-
tection switching against master clock failure.
A further input is provided for an optional standby
SEC clock. The ACS8515 is fully compliant with
the required specifications and standards.
The ACS8515 can perform frequency translation
from a SEC input clock distributed along a back
plane to a different local line card clock, e.g.
8 kHz distributed on the back plane and
19.44 MHz generated on the line cards.
An SPI
providing access to the configuration and status
registers for device setup.
The ACS8515 can utilise either a low cost XO
oscillator module, or a TCXO with full tempera-
ture calibration - as required by the application.
Rev2.1 adds choice of edge alignment for 8kHz
input, as well as a low jitter n x E1/DS1 output
mode. Other minor changes are made, with all
described in Appendix A.
Revision 2.01/December 2005 Semtech Corp.
Figure 1. Simple Block Diagram
Figure 1. Simple Block Diagram
Figure 1. Simple Block Diagram
Figure 1. Simple Block Diagram
Figure 1. Simple Block Diagram
ADVANCED COMMUNICATIONS
Block Diagram
Block Diagram
Block Diagram
Block Diagram
Block Diagram
1.544/2.048MHz
Description
Description
Description
Description
Description
3 x SEC Input
Master/Slave
155.52MHz
+ Standby:
19.44MHz
38.88MHz
51.84MHz
77.76MHz
N x 8kHz
6.48MHz
MFrSync
(1)
compatible serial port is incorporated,
3xSEC
MFrSync
TCXO or XO
Chip Clock
Input
Ports
Generator
Monitors
Priority
Table
Register
Set
Frequency Synthesis
DPLL
•Suitable for Stratum 3, 4E and 4 SONET
•Meets AT&T, ITU-T, ETSI and Telcordia
•Three SEC input clocks, from 2 kHz to
•Generates two SEC output clocks, up to
•Frequency translation of SEC input clock to a
•Robust input clock source frequency and
•Supports Free-run, Locked and Holdover
•Automatic ‘hit-less’ source switchover on loss
•External force fast switch between SEC inputs
•Phase build out for output clock phase
•SPI
•Programmable wander and jitter tracking
•Single +3.3 V operation. +5 V I/O compatible
•Operating temperature (ambient) -40°C to
•Available in 64 pin LQFP package
•Lead (pb)-free version available (ACS8515
(1) SPI is a trademark of Motorola Corporation
+85°C
Features
Features
Features
Features
Features
different local line card clock
activity monitoring on all inputs
of input
SPI Compatible Serial
for SONET or SDH Network Elements
or SDH Equipment Clock (SEC) applications
155.52 MHz
311.04 MHz
modes of operation
attenuation 0.1 Hz to 20 Hz
Rev2.1T) RoHS and WEEE compliant.
Microprocessor Port
specifications
continuity during input switchover
ACS8515 Rev2.1 LC/P
(1)
compatible serial microprocessor interface
L L L L L ine C C C C C ard P P P P P rotection S S S S S witch
Frequency
Dividers
APLL
MFrSync
2xSEC
Output
FrSync
Ports
www.semtech.com
FINAL

Related parts for ACS8515REV2.1T

ACS8515REV2.1T Summary of contents

Page 1

ADVANCED COMMUNICATIONS Description Description Description Description Description The ACS8515 is a highly integrated, single-chip solution for ‘hit-less’ protection switching of SEC clocks from Master and Slave SETS clockcards in a SONET or SDH Network Element. The ACS8515 has fast activity ...

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ADVANCED COMMUNICATIONS Table of Cont able of Cont able of Cont ents ents able of Cont able of Contents ents ents List of Sections List of Sections List of Sections List of Sections List of Sections ...

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ADVANCED COMMUNICATIONS List of Figures List of Figures List of Figures List of Figures List of Figures Figure 1. Simple Block Diagram .............................................................................................................................................................. 1 Figure 2. ACS8515 Pin Diagram ............................................................................................................................................................. 4 Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1) .................................................................................................................... 11 ...

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ADVANCED COMMUNICATIONS Pin Diagram Pin Diagram Pin Diagram Pin Diagram Pin Diagram Figure 2. ACS8515 Pin Diagram Figure 2. ACS8515 Pin Diagram Figure 2. ACS8515 Pin Diagram Figure 2. ACS8515 Pin Diagram Figure 2. ACS8515 Pin Diagram 1 AGND 2 ...

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ADVANCED COMMUNICATIONS Pin Descriptions Pin Descriptions Pin Descriptions Pin Descriptions Pin Descriptions Table 1. Power Pins Table 1. Power Pins Table 1. Power Pins Table 1. Power Pins Table 1. Power Pins ...

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ADVANCED COMMUNICATIONS Table 3. Other Pins Table 3. Other Pins Table 3. Other Pins Table 3. Other Pins Table 3. Other Pins ...

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ADVANCED COMMUNICATIONS Table 3 (continued). Table 3 (continued). Table 3 (continued). Table 3 (continued). Table 3 (continued ...

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ADVANCED COMMUNICATIONS +/- 50 ppm adjustment would be sufficient to cope with most crystals, in fact the range is an order of magnitude larger due to the use of two 8 bit register locations. The setting of the conf_nominal_frequency register ...

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ADVANCED COMMUNICATIONS Table 4. Input Reference Source Selection and Group Allocation Table 4. Input Reference Source Selection and Group Allocation Table 4. Input Reference Source Selection and Group Allocation Table 4. Input Reference Source Selection and Group Allocation Table 4. ...

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ADVANCED COMMUNICATIONS PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz. The choice of PECL or LVDS compatibility is programmed via the cnfg_differential_inputs register. Unused PECL/LVDS differential inputs should be fixed with one input high ...

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ADVANCED COMMUNICATIONS The registers sts_curr_inc_offset (address 0C, 0D, 07) report the frequency of the DPLL with respect to the external TCXO frequency. This bit signed number with one LSB representing 0.0003 ppm (range of +/- 80 ppm). ...

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ADVANCED COMMUNICATIONS Figure 4. Minimum Input Jitter Tolerance (DS1/E1) Figure 4. Minimum Input Jitter Tolerance (DS1/E1) Figure 4. Minimum Input Jitter Tolerance (DS1/E1) Figure 4. Minimum Input Jitter Tolerance (DS1/E1) Figure 4. Minimum Input Jitter Tolerance (DS1/E1) (for inputs supporting ...

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ADVANCED COMMUNICATIONS Output Wander and Jitter Output Wander and Jitter Output Wander and Jitter Output Wander and Jitter Output Wander and Jitter Wander and jitter present on the output clocks are dependent on: 1. The magnitude of wander and jitter ...

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ADVANCED COMMUNICATIONS Figure 5. Wander and Jitter Transfer Measured Characteristics Figure 5. Wander and Jitter Transfer Measured Characteristics Figure 5. Wander and Jitter Transfer Measured Characteristics Figure 5. Wander and Jitter Transfer Measured Characteristics Figure 5. Wander and Jitter Transfer ...

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ADVANCED COMMUNICATIONS Figure 6. Maximum Time Interval Error of T Figure 6. Maximum Time Interval Error of T Figure 6. Maximum Time Interval Error of T Figure 6. Maximum Time Interval Error of T Figure 6. Maximum Time Interval Error ...

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ADVANCED COMMUNICATIONS 2. ETSI 300 462-5, Section 9.2, requires that the long- term phase error in the Holdover mode should not exceed {(a1+a2)S+0.5bS where ns/s (allowance for initial frequency offset 2000 ns/s (allowance for temperature ...

Page 17

ADVANCED COMMUNICATIONS Configuration Registers Configuration Registers Configuration Registers Configuration Registers Configuration Registers Each configuration register reverts to a default value on power-up or following a reset. Most default values are fixed, but some will be pin- settable. All configuration registers ...

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ADVANCED COMMUNICATIONS Register Map Register Map Register Map Register Map Register Map Shaded areas in the map are ‘don’t care’ and writing either will not affect any function of the device. Bits labelled ‘Set to 0’ or ...

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ADVANCED COMMUNICATIONS Table 10. Register Map (continued). Table 10. Register Map (continued). Table 10. Register Map (continued). Table 10. Register Map (continued). Table 10. Register Map (continued ...

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ADVANCED COMMUNICATIONS Table 10. Register Map (continued). Table 10. Register Map (continued). Table 10. Register Map (continued). Table 10. Register Map (continued). Table 10. Register Map (continued ...

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ADVANCED COMMUNICATIONS Register Map Description Register Map Description Register Map Description Register Map Description Register Map Description Table 11. Register Map Description Table 11. Register Map Description Table 11. Register Map Description Table 11. Register Map Description Table 11. Register ...

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ADVANCED COMMUNICATIONS Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued ...

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ADVANCED COMMUNICATIONS Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued ...

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ADVANCED COMMUNICATIONS Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued ...

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ADVANCED COMMUNICATIONS Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued ...

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ADVANCED COMMUNICATIONS Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued ...

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ADVANCED COMMUNICATIONS Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued ...

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ADVANCED COMMUNICATIONS Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued). Table 11. Register Map Description (continued ...

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ADVANCED COMMUNICATIONS Selection of Input Reference Clock Selection of Input Reference Clock Selection of Input Reference Clock Selection of Input Reference Clock Selection of Input Reference Clock ...

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ADVANCED COMMUNICATIONS Ultra Fast Switching Ultra Fast Switching Ultra Fast Switching Ultra Fast Switching Ultra Fast Switching A reference source is normally disqualified after the leaky bucket monitor thresholds have been crossed. An option for a faster disqualification has been ...

Page 31

ADVANCED COMMUNICATIONS the alarm is cleared depends upon the decay rate and the alarm-clearing threshold. On the alarm-setting side, if several events occur close together, each event adds to the amplitude and the alarm will be triggered quickly; if events ...

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ADVANCED COMMUNICATIONS disqualified for phase, frequency, inactivity or if the source is outside the DPLL lock range. If the currently selected reference source is disqualified, the next highest priority, active reference source is selected. Restoration of repaired reference sources is ...

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ADVANCED COMMUNICATIONS Lost-Phase Mode Lost-Phase Mode Lost-Phase Mode Lost-Phase Mode Lost-Phase Mode Lost-phase mode is entered when the current phase error, as measured within the DPLL, is larger than a preset limit (see register 04, bits 5:3 result ...

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ADVANCED COMMUNICATIONS Figure 10. Automatic Mode Control State Diagram Figure 10. Automatic Mode Control State Diagram Figure 10. Automatic Mode Control State Diagram Figure 10. Automatic Mode Control State Diagram Figure 10. Automatic Mode Control State Diagram (1)Reset (4) valid ...

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ADVANCED COMMUNICATIONS Electrical Specification Electrical Specification Electrical Specification Electrical Specification Electrical Specification Important Note Important Note Important Note Important Note Important Note: The ‘Absolute Maximum Ratings’ are stress ratings only, and functional operation of the device at conditions other than ...

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ADVANCED COMMUNICATIONS Table 15. DC Characteristics: TTL Input Pad with Internal Pull-up Table 15. DC Characteristics: TTL Input Pad with Internal Pull-up Table 15. DC Characteristics: TTL Input Pad with Internal Pull-up Table 15. DC Characteristics: TTL Input Pad with ...

Page 37

ADVANCED COMMUNICATIONS Table 18. DC Characteristics: PECL Input/Output Pad Table 18. DC Characteristics: PECL Input/Output Pad Table 18. DC Characteristics: PECL Input/Output Pad Table 18. DC Characteristics: PECL Input/Output Pad Table 18. DC Characteristics: PECL Input/Output Pad Across operating conditions, ...

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ADVANCED COMMUNICATIONS Figure 11. Recommended Line Termination for PECL Input/Output Ports Figure 11. Recommended Line Termination for PECL Input/Output Ports Figure 11. Recommended Line Termination for PECL Input/Output Ports Figure 11. Recommended Line Termination for PECL Input/Output Ports Figure 11. ...

Page 39

ADVANCED COMMUNICATIONS Figure 12. Recommended Line Termination for LVDS Input/Output Ports Figure 12. Recommended Line Termination for LVDS Input/Output Ports Figure 12. Recommended Line Termination for LVDS Input/Output Ports Figure 12. Recommended Line Termination for LVDS Input/Output Ports Figure 12. ...

Page 40

ADVANCED COMMUNICATIONS Table 21. DC Characteristics: Output Jitter Generation (Test definition G.812) Table 21. DC Characteristics: Output Jitter Generation (Test definition G.812) Table 21. DC Characteristics: Output Jitter Generation (Test definition G.812) Table 21. DC Characteristics: Output Jitter Generation (Test ...

Page 41

ADVANCED COMMUNICATIONS Table 23. DC Characteristics: Output Jitter Generation (Test definition GR-253-CORE) Table 23. DC Characteristics: Output Jitter Generation (Test definition GR-253-CORE) Table 23. DC Characteristics: Output Jitter Generation (Test definition GR-253-CORE) Table 23. DC Characteristics: Output Jitter Generation (Test ...

Page 42

ADVANCED COMMUNICATIONS Table 25. DC Characteristics: Output Jitter Generation (Test definition G.742) Table 25. DC Characteristics: Output Jitter Generation (Test definition G.742) Table 25. DC Characteristics: Output Jitter Generation (Test definition G.742) Table 25. DC Characteristics: Output Jitter Generation (Test ...

Page 43

ADVANCED COMMUNICATIONS Notes for tables 20 - 227 Notes for tables 20 - 227 Notes for tables 20 - 227 Notes for tables 20 - 227 Notes for tables 20 - 227 Note 1. Filter used is that defined by ...

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ADVANCED COMMUNICATIONS Microprocessor Interface Timing Microprocessor Interface Timing Microprocessor Interface Timing Microprocessor Interface Timing Microprocessor Interface Timing The device has a Serial microprocessor interface. The combined minimum High and Low times for SCLK define the maximum clock rate. For Write ...

Page 45

ADVANCED COMMUNICATIONS Table 28. Read Access Timing Table 28. Read Access Timing Table 28. Read Access Timing Table 28. Read Access Timing Table 28. Read Access Timing ...

Page 46

ADVANCED COMMUNICATIONS Package Information Package Information Package Information Package Information Package Information Figure 16. LQFP Package Figure 16. LQFP Package Figure 16. LQFP Package Figure 16. LQFP Package Figure 16. LQFP Package ...

Page 47

ADVANCED COMMUNICATIONS Table 30. 64 Pin LQFP Package Dimension Data (for use with Figure 16) Table 30. 64 Pin LQFP Package Dimension Data (for use with Figure 16) Table 30. 64 Pin LQFP Package Dimension Data (for use with Figure ...

Page 48

ADVANCED COMMUNICATIONS Application Information Application Information Application Information Application Information Application Information Figure 18. Simplified Application Schematic Figure 18. Simplified Application Schematic Figure 18. Simplified Application Schematic Figure 18. Simplified Application Schematic Figure 18. Simplified Application Schematic Revision 2.01/December 2005 ...

Page 49

ADVANCED COMMUNICATIONS Appendix A Rev2.1 Changes Described Appendix A Rev2.1 Changes Described Appendix A Rev2.1 Changes Described Appendix A Rev2.1 Changes Described Appendix A Rev2.1 Changes Described Summary Summary Summary Summary Summary This section summarizes the minor changes and improvements ...

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ADVANCED COMMUNICATIONS Ordering Information Ordering Information Ordering Information Ordering Information Ordering Information ...

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