ACS8525ALC SEMTECH [Semtech Corporation], ACS8525ALC Datasheet
ACS8525ALC
Related parts for ACS8525ALC
ACS8525ALC Summary of contents
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ADVANCED COMMS & SENSING ADVANCED COMMUNICATIONS Description The ACS8525A is a highly integrated, single-chip solution for “Hit-less” protection switching of SEC (SDH/SONET Equipment Clock) + Sync clock “Groups”, from Master and Slave SETS clock cards and a third (Stand-by) source, ...
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ADVANCED COMMS & SENSING Table of Contents Section Description ................................................................................................................................................................................................. 1 Block Diagram ............................................................................................................................................................................................1 Features .....................................................................................................................................................................................................1 Pin Diagram ...............................................................................................................................................................................................4 Pin Description ...........................................................................................................................................................................................5 Introduction ................................................................................................................................................................................................6 General Description ...................................................................................................................................................................................7 Inputs .................................................................................................................................................................................................7 Preconfiguring Inputs ...............................................................................................................................................................8 PECL/LVDS Input Port Selection .............................................................................................................................................9 Input Locking Frequency ...
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ADVANCED COMMS & SENSING Section Electrical Specifications ......................................................................................................................................................................... 98 JTAG ................................................................................................................................................................................................ 98 Over-voltage Protection ................................................................................................................................................................. 98 ESD Protection ............................................................................................................................................................................... 98 Latchup Protection ......................................................................................................................................................................... 98 Maximum Ratings .......................................................................................................................................................................... 99 Operating Conditions ..................................................................................................................................................................... 99 DC Characteristics ......................................................................................................................................................................... 99 Jitter Performance ....................................................................................................................................................................... 103 ...
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ADVANCED COMMS & SENSING Pin Diagram Figure 2 ACS8525A Pin Diagram Line Card Protection Switch for SONET/SDH Systems Revision 1.00/September 2007 © Semtech Corp. ACS8525A LC/P FINAL Page 4 DATASHEET www.semtech.com ...
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ADVANCED COMMS & SENSING Pin Description Table 1 Power Pins Pin Number Symbol I VD1+, VD2 VD3+ 22 VDD_DIFF P 27 VDDCLMP P 32, 36, VDD1, VDD2, P 38, 39, VDD3, VDD4, 45, 46, VDD5, VDD6, ...
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ADVANCED COMMS & SENSING Table 3 Other Pins (cont...) Pin Number Symbol I/O 18 MFrSync O 19, O1POS O1NEG 23, SEC1_POS SEC1_NEG 25, SEC2_POS SEC2_NEG 28 SYNC1 I 29 SEC1 I 30 SEC2 I ...
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ADVANCED COMMS & SENSING The ACS8525A is a highly integrated, single-chip solution for “Hit-less” protection switching of SEC + Sync clock “Groups”, from Master and Slave SETS clock cards and a third (Stand-by) source, for Line Cards in a SONET ...
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ADVANCED COMMS & SENSING on page 98 for more information on electrical compatibility. Input frequencies supported range from 2 kHz to 155.52 MHz. Common E1, DS1, OC-3 and sub-divisions are supported as spot frequencies that the DPLLs will directly lock ...
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ADVANCED COMMS & SENSING PECL/LVDS Input Port Selection The choice of PECL or LVDS compatibility is programmed via the cnfg_differential_inputs register. Unused PECL differential inputs should be fixed with one input High (VDD) and the other input Low (GND), or ...
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ADVANCED COMMS & SENSING dynamics between the selected clock and the other reference clocks. Anomalies occurring on non-selected SECs affect only that source's suitability for selection, whereas anomalies occurring on the selected clock could have a detrimental impact on the ...
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ADVANCED COMMS & SENSING Disqualification of a non-selected SEC is based on inactivity noted by the Activity Monitors. The currently selected SEC can be disqualified for being out-of phase, inactive the source is outside the DPLL lock range. ...
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ADVANCED COMMS & SENSING sources are active and valid, the source with the highest programmed priority is selected, but if this source fails, the next-highest source is selected, and so on. Restoration of repaired SECs is handled carefully to avoid ...
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ADVANCED COMMS & SENSING device in the JTAG scan chain, the implementation should be such that a logic change caused by the action of the interrupt on the TDI input should not effect the operation when JTAG is not active. ...
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ADVANCED COMMS & SENSING via register control, which provides a range of output frequencies and levels of jitter performance. The DPLLs give a stable and consistent level of performance that can be easily programmed for different dynamic behavior or operating ...
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ADVANCED COMMS & SENSING Figure 5 PLL Block Diagram DPLL2_meas_ sts_current_phase DPLL1_ph DPLL2 Reference Input 1 PFD and for phase measurement Loop Filter only 0 Locking DPLL2 Frequency 8 kHz sts_current_phase DPLL1 PFD and Reference Input Loop Filter Locking Frequency ...
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ADVANCED COMMS & SENSING Output DFS block (offering 77.76 MHz, 12E1, 16E1, 24DS1 or 16DS1). The frequency from APLL1 is four times its input frequency i.e. 311.04 MHz when used with a 77.76 MHz input. APLL1 is subsequently divided by ...
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ADVANCED COMMS & SENSING APLLs There are three main APLLs. APLL1 and APLL2 provide a lower final output jitter reducing the 4.9 ns p-p jitter from the digital down to 500 ps p-p and 60 ps rms as typical final ...
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ADVANCED COMMS & SENSING Figure 6 DPLL1 Jitter Transfer Characteristic, (Freq = 1.544 MHz, Jitter = 0.2 UI p-p, Damping Factor = 5) Damping Factor Programmability The DPLL damping factor is set by default to provide a maximum wander gain ...
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ADVANCED COMMS & SENSING An Early/Late phase detector for fine resolution A multi-cycle phase detector for large input jitter tolerance (up to 8191 UI), which captures and remembers phase differences of many cycles between input and feedback clocks. The phase ...
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ADVANCED COMMS & SENSING When PBO is enabled, PBO can also be frozen (at the current offset setting). The device will then ignore any further PBO events occurring on any subsequent reference switch, and maintain the current phase offset. If ...
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ADVANCED COMMS & SENSING Output Phase Adjustment Programmable Input to Output phase offset adjustment, ±200 ns resolution step size (Reg. 70 and 71) Programmable mean offset on Phase Build-out event (PBO phase offset on source switching) - disturbance ...
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ADVANCED COMMS & SENSING Outputs The ACS8525A delivers four output signals on the following ports: Two clocks, one each on ports Output O1 and Output O2; and two Sync signals, on ports FrSync and MFrSync. Output O1 and Output O2 ...
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ADVANCED COMMS & SENSING Table 7 Output Frequency Selection (cont...) Frequency (MHz, unless stated otherwise) 1.536 1.536 1.544 1.544 1.544 via Digital1 or Digital2 (not Output O1) 1.544 via Digital1 or Digital2 (not Output O1) 2.048 2.048 2.048 2.048 2.048 ...
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ADVANCED COMMS & SENSING Table 7 Output Frequency Selection (cont...) Frequency (MHz, unless stated otherwise) 4.86 5.728 6.144 6.144 6.144 6.176 6.176 6.176 6.176 via Digital1 or Digital2 (not Output O1) 6.176 via Digital1 or Digital2 (not Output O1) 6.48 ...
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ADVANCED COMMS & SENSING Table 7 Output Frequency Selection (cont...) Frequency (MHz, unless stated otherwise) 12.352 12.352 via Digital1 or Digital2 (not Output O1) 12.352 via Digital1 or Digital2 (not Output O1) 16.384 16.384 16.384 16.384 16.384 via Digital1 or ...
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ADVANCED COMMS & SENSING Table 7 Output Frequency Selection (cont...) Frequency (MHz, unless stated otherwise) 34.368 37.056 37.056 37.056 38.88 38.88 38.88 44.736 49.152 (Output O1 only) 49.408 (Output O1 only) 51.84 51.84 65.536 (Output O1 only) 68.736 74.112 (Output ...
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ADVANCED COMMS & SENSING Table 8 Frequency Divider Look-up Transmission Rate APLL Frequency OC-N Rates 311.04 E3 274.944 DS3 178.944 24DS1 148.224 16E1 131.072 16DS1 98.816 12E1 98.304 Note...All frequencies in MHz Table 9 APLL1 Frequencies APLL1 Frequency Synthesis/MUX setting ...
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ADVANCED COMMS & SENSING Table 10 APLL2 Frequencies (cont...) APLL2 DPLL Mode DPLL2 Forward Frequency DFS Frequency 98.816 MHz DPLL2-16DS1 24.704 274.944 MHz DPLL2-E3 68.736 (2*34.368) 178.944 MHz DPLL2-DS3 44.736 98.304 MHz DPLL1-12E1 131.072 MHz DPLL1-16E1 148.224 MHz DPLL1-24DS1 98.816 ...
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ADVANCED COMMS & SENSING “Digital” Frequencies Table 11, “O1 and O2 Output Frequency Selection,” lists Digital1 and Digital2 as available for selection. Digital1 is a single frequency selected from the range shown in Table 12. Digital2 is another single frequency ...
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ADVANCED COMMS & SENSING Operating Modes (States) of the Device The ACS8525A has three primary modes of operation, or operating states: Free-Run, Locked and Digital Holdover. These are supported by three secondary, temporary modes (Pre-Locked, Lost-Phase and Pre-Locked2). Refer to ...
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ADVANCED COMMS & SENSING Figure 8 Automatic Mode Control State Diagram (DPLL1) (1) Reset (3) no valid standby ref (main ref invalid or out of lock > 100s (4) valid standby ref & [main ref invalid or (higher-priority ref valid ...
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ADVANCED COMMS & SENSING Pre-locked2 Mode This state is very similar to the Pre-locked state entered from the Digital Holdover state when an input SEC has been selected and applied to the phase locked loop also ...
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ADVANCED COMMS & SENSING averaged or filtered with attenuation point at approximately 100 Hz. Measuring Phase Between Master and Slave/Stand-by SEC Sources The phase can be measured between the selected SEC input to DPLL1 and either of ...
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ADVANCED COMMS & SENSING Figure 9 External Sync Input Phase Control (Reg.7B Bits [1:0]) Sync Input On Target SEC Input SEC Output Sync Input Sync Output As with all frequencies generated at the outputs of the ACS8525A, the Sync outputs ...
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ADVANCED COMMS & SENSING either 19.44 MHz (when the current locked to reference is 19.44 MHz) or 38.88 MHz (all other frequencies). This would allow, for instance, a 19.44 MHz and 2 kHz pair to be used for Line Card ...
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ADVANCED COMMS & SENSING Figure 10 Read Access Timing for SERIAL Interface CLKE = 0; SDO data is clocked out on the rising edge of SCLK CSB t su2 SCLK t su1 ...
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ADVANCED COMMS & SENSING Figure 11 Write Access Timing for SERIAL Interface CSB t su2 SCLK t su1 R/W SDI Output not driven, pulled low by internal resistor SDO Table 14 Write ...
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ADVANCED COMMS & SENSING Register Map Each Register, or register group, is described in the following Register Map (Table 15) and subsequent Register Description Tables. Register Organization The ACS8525A LC/P uses a total of 91 eight-bit register locations, identified by ...
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ADVANCED COMMS & SENSING Table 15 Register Map Register Name RO = Read Only 7 (MSB) R/W = Read/Write chip_id (RO chip_revision (RO test_register1 (R/ Phase_alarm test_register2 (R/ sts_interrupts (R/W) ...
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ADVANCED COMMS & SENSING Table 15 Register Map (cont...) Register Name RO = Read Only 7 (MSB) R/W = Read/Write cnfg_DPLL_freq_limit (R/W) [9: cnfg_interrupt_mask (R/W) [7: Set to 0 [15: operating_ mode [23:16] 45 ...
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ADVANCED COMMS & SENSING Table 15 Register Map (cont...) Register Name RO = Read Only 7 (MSB) R/W = Read/Write cnfg_phase_loss_coarse_limit 74 85 coarse_lim_ (R/W) phaseloss_en cnfg_ip_noise_window (R/ ip_noise_ window_en sts_current_phase (RO) [7: [15: ...
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ADVANCED COMMS & SENSING Register Descriptions 00 Address (hex): Register Name chip_id Bit 7 Bit 6 Bit No. Description [7:0] chip_id Least significant byte of the 2-byte device ID. 01 Address (hex): Register Name chip_id Bit 7 Bit 6 Bit ...
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ADVANCED COMMS & SENSING 03 Address (hex): Register Name test_register1 Bit 7 Bit 6 phase_alarm disable_180 Bit No. Description 7 phase_alarm (phase alarm (R/O)) Instantaneous result from DPLL1. 6 disable_180 Normally the DPLL will try to lock to the nearest ...
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ADVANCED COMMS & SENSING 05 Address (hex): Register Name sts_interrupts Bit 7 Bit 6 status_SEC2_ DIFF Bit No. Description [7:6] Not used. 5 status_SEC2_DIFF Interrupt indicating that input SEC2 DIFF has become valid (if it was invalid), or invalid (if ...
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ADVANCED COMMS & SENSING 06 (cont...) Address (hex): Register Name sts_interrupts Bit 7 Bit 6 operating_ DPLL1_ mode main_ref_failed Bit No. Description 6 DPLL1_main_ref_failed Interrupt indicating that input to the DPLL1 has failed. This interrupt will be raised after 2 ...
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ADVANCED COMMS & SENSING 08 Address (hex): Register Name sts_interrupts Bit 7 Bit 6 Sync_alarm_ int Bit No. Description 7 Sync_alarm_int Interrupt indicating that the selected Sync input monitor has hit its alarm limit. Latched until reset by software writing ...
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ADVANCED COMMS & SENSING 09 (cont...) Address (hex): Register Name sts_operating_mode Bit 7 Bit 6 Sync_alarm DPLL2_Lock DPLL1_freq_ soft_alarm Bit No. Description 6 DPLL2_Lock Reports current phase lock status of DPLL2. DPLL2 does not have the same state machine as ...
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ADVANCED COMMS & SENSING 09 (cont...) Address (hex): Register Name sts_operating_mode Bit 7 Bit 6 Sync_alarm DPLL2_Lock DPLL1_freq_ soft_alarm Bit No. Description 5 DPLL1_freq_soft_alarm DPLL1 has a programmable frequency limit and “soft” alarm limit. The frequency limit is the extent ...
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ADVANCED COMMS & SENSING 0A Address (hex): Register Name sts_priority_table Bit 7 Bit 6 Highest priority validated source Bit No. Description [7:4] Highest priority validated source Reports the input channel number of the highest priority validated source. [3:0] Currently selected ...
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ADVANCED COMMS & SENSING 0B Address (hex): Register Name sts_priority_table Bit 7 Bit highest priority validated source Bit No. Description rd [7:4] 3 highest priority validated source Reports the input channel number of the 3 priority validated ...
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ADVANCED COMMS & SENSING 0C Address (hex): Register Name sts_current_DPLL_frequency [7:0] Bit 7 Bit 6 Bit No. Description [7:0] Bits [7:0] of sts_current_DPLL_frequency *When Bit 4 (DPLL1_DPLL2_select) of Reg. 4B (cnfg_registers_source_select the frequency for DPLL1 is reported. When ...
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ADVANCED COMMS & SENSING 0E Address (hex): Register Name sts_sources_valid Bit 7 Bit 6 SEC2 DIFF Bit No. Description [7:6] Not used. 5 SEC2 DIFF Bit indicating if SEC2 DIFF is valid. The input is valid if it has no ...
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ADVANCED COMMS & SENSING 11 Address (hex): Register Name sts_reference_sources SEC1 & SEC2 TTL Bit 7 Bit 6 Reg. 11: Status of SEC2 TTL Input Reg. 12: Status of SEC2 DIFF Input Bit No. Description [7:6] & [3:2] Not Used ...
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ADVANCED COMMS & SENSING 19 (cont...) Address (hex): Register Name cnfg_ref_selection_priority SEC1 & SEC2 TTL Bit 7 Bit 6 programmed_priority_SEC2 TTL Bit No. Description [3:0] programmed_priority_SEC1 TTL This 4-bit value represents the relative priority of input SEC1 TTL. The smaller ...
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ADVANCED COMMS & SENSING 1C Address (hex): Register Name cnfg_ref_selection_priority SEC3 Bit 7 Bit 6 Bit No. Description [7:4] Not used. [3:0] cnfg_ref_selection_priority_9 This 4-bit value represents the relative priority of input SEC3. The smaller the number, the higher the ...
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ADVANCED COMMS & SENSING 22 (cont...) Address (hex): Register Name cnfg_ref_source_frequency <input> For Reg. 22, <input> = SEC1 TTL Bit 7 Bit 6 divn_<input> lock8k_<input> Bit No. Description [3:0] reference_source_frequency_<input> Programs the frequency of the SEC connected to input <input>. ...
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ADVANCED COMMS & SENSING 32 (cont...) Address (hex): Register Name cnfg_operating_mode Bit 7 Bit 6 Bit No. Description [2:0] DPLL1_operating_mode This field is used to control the state of the internal finite state machine controlling DPLL1. A value of zero ...
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ADVANCED COMMS & SENSING 34 Address (hex): Register Name cnfg_input_mode Bit 7 Bit 6 auto_extsync_ phalarm_time- XO_edge en out Bit No. Description 7 auto_extsync_en Bit to automatically disable the external Frame Sync input following a source switch. 6 phalarm_timeout Bit ...
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ADVANCED COMMS & SENSING 35 Address (hex): Register Name cnfg_DPLL2_path Bit 7 Bit 6 DPLL2_dig_ feedback Bit No. Description 7 Not used. 6 DPLL2_dig_feedback Bit to select digital feedback mode for DPLL2. [5:0] Not used. 36 Address (hex): Register Name ...
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ADVANCED COMMS & SENSING 38 Address (hex): Register Name cnfg_dig_outputs_sonsdh Bit 7 Bit 6 dig2_sonsdh dig1_sonsdh Bit No. Description 7 Not used. 6 dig2_sonsdh Selects whether the frequencies generated by the Digital2 frequency generator are SONET derived or SDH. *Default ...
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ADVANCED COMMS & SENSING 3A Address (hex): Register Name cnfg_differential_output Bit 7 Bit 6 Bit No. Description [7:2] Not used. [1:0] Output O1_LVDS_PECL Selection of the electrical compatibility of Output O1 between 3 V PECL and 3 V LVDS. 3B ...
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ADVANCED COMMS & SENSING 3C Address (hex): Register Name cnfg_nominal_frequency [7:0] Bit 7 Bit 6 Bit No. Description [7:0] cnfg_nominal_frequency_value[7:0]. 3D Address (hex): Register Name cnfg_nominal_frequency [15:8] Bit 7 Bit 6 Bit No. Description [7:0] cnfg_nominal_frequency_value[15:8] This register is used ...
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ADVANCED COMMS & SENSING 41 Address (hex): Register Name cnfg_DPLL_freq_limit [7:0] Bit 7 Bit 6 Bit No. Description [7:0] Bits [7:0] of cnfg_DPLL_freq_limit This register defines the extent of frequency offset to which either the DPLL1 or DPLL2 will track ...
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ADVANCED COMMS & SENSING 43 Address (hex): Register Name cnfg_interrupt_mask [7:0] Bit 7 Bit 6 SEC2 DIFF Bit No. Description [7:6] Not used. 5 SEC2 DIFF Mask bit for input SEC2 DIFF interrupt. 4 SEC1 DIFF Mask bit for input ...
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ADVANCED COMMS & SENSING 45 Address (hex): Register Name cnfg_interrupt_mask [23:16] Bit 7 Bit 6 Sync_ip_alarm Bit No. Description 7 Sync_ip_alarm Mask bit for Sync_ip_alarm interrupt. [6:0] Not used. 46 Address (hex): Register Name cnfg_freq_divn [7:0]. Bit 7 Bit 6 ...
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ADVANCED COMMS & SENSING 47 (cont...) Address (hex): Register Name cnfg_freq_divn [13:8] Bit 7 Bit 6 Bit No. Description [5:0] divn_value[13:8] This register, in conjunction with Reg. 46 (cnfg_freq_divn) represents the integer value by which to divide inputs that use ...
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ADVANCED COMMS & SENSING 48 (cont...) Address (hex): Register Name cnfg_monitors Bit 7 Bit 6 los_flag_on_ ultra_fast_ TDO switch Bit No. Description 4 ext_switch Bit to enable external switching mode. When in external switching mode, the device is only allowed ...
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ADVANCED COMMS & SENSING 4B Address (hex): Register Name cnfg_registers_source_select Bit 7 Bit 6 Bit No. Description [7:5] Not used. 4 DPLL1_DPLL2_select Bit to select between many of the registers associated with DPLL1 or DPLL2 e.g. frequency registers. [3:0] Not ...
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ADVANCED COMMS & SENSING 50 Address (hex): Register Name cnfg_upper_threshold_0 Bit 7 Bit 6 upper_threshold_0_value (Activity alarm, Config. 0, Leaky Bucket - set threshold) Bit No. Description [7:0] upper_threshold_0_value The Leaky Bucket operates on a 128 ms cycle. If, during ...
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ADVANCED COMMS & SENSING 52 Address (hex): Register Name cnfg_bucket_size_0 Bit 7 Bit 6 bucket_size_0_value (Activity alarm, Config. 0, Leaky Bucket - size) Bit No. Description [7:0] bucket_size_0_value The Leaky Bucket operates on a 128 ms cycle. If, during a ...
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ADVANCED COMMS & SENSING 54 Address (hex): Register Name cnfg_upper_threshold_1 Bit 7 Bit 6 upper_threshold_1_value (Activity alarm, Config. 1, Leaky Bucket - set threshold) Bit No. Description [7:0] upper_threshold_1_value The Leaky Bucket operates on a 128 ms cycle. If, during ...
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ADVANCED COMMS & SENSING 56 Address (hex): Register Name cnfg_bucket_size_1 Bit 7 Bit 6 bucket_size_1_value (Activity alarm, Config. 1, Leaky Bucket - size) Bit No. Description [7:0] bucket_size_1_value The Leaky Bucket operates on a 128 ms cycle. If, during a ...
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ADVANCED COMMS & SENSING 58 Address (hex): Register Name cnfg_upper_threshold_2 Bit 7 Bit 6 upper_threshold_2_value (Activity alarm, Config. 2, Leaky Bucket - set threshold) Bit No. Description [7:0] upper_threshold_2_value The Leaky Bucket operates on a 128 ms cycle. If, during ...
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ADVANCED COMMS & SENSING 5A Address (hex): Register Name cnfg_bucket_size_2 Bit 7 Bit 6 bucket_size_2_value (Activity alarm, Config. 2, Leaky Bucket - size) Bit No. Description [7:0] bucket_size_2_value The Leaky Bucket operates on a 128 ms cycle. If, during a ...
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ADVANCED COMMS & SENSING 5C Address (hex): Register Name cnfg_upper_threshold_3 Bit 7 Bit 6 upper_threshold_3_value (Activity alarm, Config. 3, Leaky Bucket - set threshold) Bit No. Description [7:0] upper_threshold_3_value The Leaky Bucket operates on a 128 ms cycle. If, during ...
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ADVANCED COMMS & SENSING 5E Address (hex): Register Name cnfg_bucket_size_3 Bit 7 Bit 6 bucket_size_3_value (Activity alarm, Config. 3, Leaky Bucket - size) Bit No. Description [7:0] bucket_size_3_value The Leaky Bucket operates on a 128 ms cycle. If, during a ...
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ADVANCED COMMS & SENSING 61 Address (hex): Register Name cnfg_output_frequency (Output O2) Bit 7 Bit 6 Bit No. Description [7:4] Not used. [3:0] output_freq_O2 Configuration of the output frequency available at Output O2. Many of the frequencies available are dependent ...
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ADVANCED COMMS & SENSING 62 Address (hex): Register Name cnfg_output_frequency (Output O1) Bit 7 Bit 6 output_freq_O1 Bit No. Description [7:4] output_freq_O1 Configuration of the output frequency available at Output O1. Many of the frequencies available are dependent on the ...
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ADVANCED COMMS & SENSING 64 Address (hex): Register Name cnfg_DPLL2_frequency Bit 7 Bit 6 Bit No. Description [7:4] Not used. [2:0] DPLL2_frequency Register to configure the frequency of operation of DPLL2. The frequency of DPLL2 will also affect the frequency ...
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ADVANCED COMMS & SENSING 65 (cont...) Address (hex): Register Name cnfg_DPLL1_frequency Bit 7 Bit 6 DPLL2_meas_ APLL2_for_ DPLL1_ph DPLL1_E1/DS1 Bit No. Description [5:4] DPLL1_freq_to_APLL2 Register to select the frequency/mode of DPLL1 which is driven to the APLL2 when selected by ...
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ADVANCED COMMS & SENSING 66 Address (hex): Register Name cnfg_DPLL2_bw Bit 7 Bit 6 Bit No. Description [7:2] Not used. [1:0] DPLL2_bandwidth Register to configure the bandwidth of DPLL2. 67 Address (hex): Register Name cnfg_DPLL1_locked_bw Bit 7 Bit 6 Bit ...
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ADVANCED COMMS & SENSING 69 (cont...) Address (hex): Register Name cnfg_DPLL1_acq_bw Bit 7 Bit 6 Bit No. Description [3:0] DPLL1_acquisition_bandwidth Register to configure the bandwidth of DPLL1 when acquiring phase lock on an input reference. Reg. 3B Bit 7 is ...
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ADVANCED COMMS & SENSING 6A (cont...) Address (hex): Register Name cnfg_DPLL2_damping Bit 7 Bit 6 DPLL2_PD2_gain_alog_8k Bit No. Description [2:0] DPLL2_damping Register to configure the damping factor of DPLL2. The bit values correspond to different damping factors, depending on the ...
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ADVANCED COMMS & SENSING 6B (cont...) Address (hex): Register Name cnfg_DPLL1_damping Bit 7 Bit 6 DPLL1_PD2_gain_alog_8k Bit No. Description [2:0] DPLL1_damping Register to configure the damping factor of DPLL1. The bit values correspond to different damping factors, depending on the ...
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ADVANCED COMMS & SENSING 6C (cont...) Address (hex): Register Name cnfg_DPLL2_PD2_gain Bit 7 Bit 6 DPLL2_PD2_ DPLL2_PD2_gain_alog gain_enable Bit No. Description [2:0] DPLL2_PD2_gain_digital Register to control the gain of Phase Detector 2 when locking to a reference in digital feedback ...
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ADVANCED COMMS & SENSING 6D (cont...) Address (hex): Register Name cnfg_DPLL1_PD2_gain Bit 7 Bit 6 DPLL1_PD2_ DPLL1_PD2_gain_alog gain_enable Bit No. Description [2:0] DPLL1_PD2_gain_digital Register to control the gain of Phase Detector 2 when locking to a reference in digital feedback ...
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ADVANCED COMMS & SENSING 71 Address (hex): Register Name cnfg_phase_offset [15:8] Bit 7 Bit 6 Bit No. Description [7:0] phase_offset_value[15:8] Register forming part of the phase offset control. If the phase offset register is written to when the DPLL is ...
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ADVANCED COMMS & SENSING 72 (cont...) Address (hex): Register Name cnfg_PBO_phase_offset Bit 7 Bit 6 Bit No. Description [5:0] PBO_phase_offset Each time a Phase Build-out event is triggered, there is an uncertainty introduced which translates ...
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ADVANCED COMMS & SENSING 73 (cont...) Address (hex): Register Name cnfg_phase_loss_fine_limit Bit 7 Bit 6 fine_limit_en noact_ph_loss narrow_en Bit No. Description 5 narrow_en (test control bit) Set to 1 (default value). [4:3] Not used. [2:0] phase_loss_fine_limit When enabled by Bit ...
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ADVANCED COMMS & SENSING 74 (cont...) Address (hex): Register Name cnfg_phase_loss_coarse_limit Bit 7 Bit 6 coarse_lim_ wide_range_en multi_ph_resp phaseloss_en Bit No. Description 6 wide_range_en To enable the device to be tolerant to large amounts of applied jitter and still do ...
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ADVANCED COMMS & SENSING 74 (cont...) Address (hex): Register Name cnfg_phase_loss_coarse_limit Bit 7 Bit 6 coarse_lim_ wide_range_en multi_ph_resp phaseloss_en Bit No. Description [3:0] phase_loss_coarse_limit Sets the range of the coarse phase loss detector and the coarse phase detector. When locking ...
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ADVANCED COMMS & SENSING 77 Address (hex): Register Name sts_current_phase [7:0] Bit 7 Bit 6 Bit No. Description [7:0] current_phase Bits [7:0] of the current phase register. See Reg. 78 sts_current_phase [15:8] for details. 78 Address (hex): Register Name sts_current_phase ...
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ADVANCED COMMS & SENSING 79 (cont...) Address (hex): Register Name cnfg_phase_alarm_timeout Bit 7 Bit 6 Bit No. Description [5:0] timeout_value Phase alarms can only be raised on an input when DPLL1 is attempting to lock to it. Once an input ...
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ADVANCED COMMS & SENSING 7A (cont...) Address (hex): Register Name cnfg_sync_pulses Bit 7 Bit 6 2k_8k_from_ DPLL2 Bit No. Description 1 2k_invert Register bit to invert the 2 kHz output from MFrSync. 0 2k_pulse Register bit to enable the 2 ...
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ADVANCED COMMS & SENSING 7B (cont...) Address (hex): Register Name cnfg_sync_phase Bit 7 Bit 6 Indep_FrSync/ Sync_OC-N_ MFrSync rates Bit No. Description 6 Sync_OC-N_rates This allows the selected Sync input to synchronize the OC-3 derived clocks in order to maintain ...
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ADVANCED COMMS & SENSING 7C Address (hex): Register Name cnfg_sync_monitor Bit 7 Bit 6 ph_offset_ramp Sync_monitor_limit Bit No. Description 7 ph_offset_ramp Register bit to force an internal phase offset calibration routine. See also Reg. 71, Cnfg_Phase_Offset. The calibration routine puts ...
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ADVANCED COMMS & SENSING 7D (cont...) Address (hex): Register Name cnfg_interrupt Bit 7 Bit 6 Bit No. Description 2 Interrupt GPO_en (Interrupt General Purpose Output). If the interrupt output pin is not required, then setting this bit will allow the ...
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ADVANCED COMMS & SENSING Electrical Specifications JTAG The JTAG connections on the ACS8525A allow a full boundary scan to be made. The JTAG implementation is [4] fully compliant to IEEE 1149.1 , with the following minor exceptions, and the user ...
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ADVANCED COMMS & SENSING Maximum Ratings Important Note: The Absolute Maximum Ratings, Table 17, are stress ratings only, and functional operation of the device at conditions other than those indicated in the Operating Conditions sections of this specification are not ...
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ADVANCED COMMS & SENSING Table 20 DC Characteristics: TTL Input Port with Internal Pull-up Across all operating conditions, unless otherwise stated Parameter V High IN V Low IN Pull-up Resistor Input Current Table 21 DC Characteristics: TTL Input Port with ...
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ADVANCED COMMS & SENSING Table 23 DC Characteristics: PECL Input/Output Port (cont...) Across all operating conditions, unless otherwise stated Parameter PECL Input Low Voltage Single-ended Input (Note iii) PECL Input High Voltage Single-ended Input (Note iii) Input High Current Input ...
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ADVANCED COMMS & SENSING Table 24 DC Characteristics: LVDS Input/Output Port Across all operating conditions, unless otherwise stated Parameter LVDS Input Voltage Range Differential Input Voltage = 100 mV LVDS Differential Input Threshold LVDS Input Differential Voltage LVDS Input Termination ...
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ADVANCED COMMS & SENSING Jitter Performance Output jitter generation measured over 60 second interval, UI p-p max measured using C-MAC E2747 12.800 MHz TCXO on ICT Flexacom tester. Table 25 Output Jitter Generation bandwidth and 8 kHz ...
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ADVANCED COMMS & SENSING Table 25 Output Jitter Generation bandwidth and 8 kHz Input (cont...) Specification [12] [9] GR-499-CORE & G824 for 1.544 MHz [12] [9] GR-499-CORE & G824 for 1.544 MHz [13] GR-1244-CORE for 1.544 MHz ...
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ADVANCED COMMS & SENSING Input/Output Timing Figure 15 Input/Output Timing with Phase Build-out Off (Typical Conditions) Input/Output 8 kHz input 8 kHz output 6.48 MHz input 6.48 MHz output 19.44 MHz input 19.44 MHz output 25.92 MHz input 25.92 MHz ...
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ADVANCED COMMS & SENSING Package Information Figure 16 LQFP Package Seating plane A1 Notes 1 The top package body may be smaller than the bottom package body by as much as 0.15 mm. ...
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ADVANCED COMMS & SENSING Thermal Conditions The device is rated for full temperature range when this package is used with a 4 layer or more PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum ...
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ADVANCED COMMS & SENSING Application Information Figure 18 Simplified Application Schematic Revision 1.00/September 2007 © Semtech Corp. ACS8525A LC/P FINAL Page 108 DATASHEET www.semtech.com ...
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ADVANCED COMMS & SENSING Abbreviations APLL Analogue Phase Locked Loop BITS Building Integrated Timing Supply DFS Digital Frequency Synthesis DPLL Digital Phase Locked Loop DS1 1544 kbit/s interface rate DTO Discrete Time Oscillator E1 2048 kbit/s interface rate I/O Input ...
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ADVANCED COMMS & SENSING Trademark Acknowledgements Semtech and the Semtech S logo are registered trademarks of Semtech Corporation. ACCUNET ® registered trademark of AT & T. C-MAC is a registered trademark of C-MAC MicroTechnology - a division of ...
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ADVANCED COMMS & SENSING Revision Status/History The Revision Status of the datasheet, as shown in the center of the datasheet header bar, may be TARGET, PRELIMINARY, or FINAL, and refers to the status of the Device (not the datasheet) within ...
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ADVANCED COMMS & SENSING Ordering Information Table 28 Parts List Part Number ACS8525A ACS8525AT Disclaimers Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical applications, and is not ...