ACS8526P SEMTECH [Semtech Corporation], ACS8526P Datasheet
ACS8526P
Related parts for ACS8526P
ACS8526P Summary of contents
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ADVANCED COMMUNICATIONS ADVANCED COMMUNICATIONS Description The ACS8526 is a highly integrated single-chip solution for protection switching between two SECs (SDH/SONET Equipment Clocks) from Master and Slave SETS clock cards, for line cards in a PDH, SONET or SDH Network Element. ...
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ADVANCED COMMUNICATIONS Table of Contents Section Description ................................................................................................................................................................................................. 1 Block Diagram............................................................................................................................................................................................ 1 Features ..................................................................................................................................................................................................... 1 Table of Contents ...................................................................................................................................................................................... 2 Pin Diagram ............................................................................................................................................................................................... 3 Pin Description........................................................................................................................................................................................... 4 Introduction................................................................................................................................................................................................ 6 General Description................................................................................................................................................................................... 6 Inputs ..................................................................................................................................................................................................6 Preconfiguring Inputs - Expected Input Frequency ...
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ADVANCED COMMUNICATIONS Pin Diagram Figure 2 ACS8526 Pin Diagram 1 AGND1 2 IC1 3 AGND2 4 VA1+ 5 LOS_ALARM 6 REFCLK 7 DGND1 8 VD1+ 9 VD2+ 10 DGND2 1 11 DGND3 12 VD3+ 13 SRCSW 14 VA2+ 15 AGND3 ...
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ADVANCED COMMUNICATIONS Pin Description Table 1 Power Pins Pin Number Symbol I VD1+, VD2 VD3+ 22 VDD_DIFF P 27 VDD5V P 32, 39, VDD1, VDD2 VDD3, 4 VA1+ P 14, 57 VA2+, VA3+ P ...
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ADVANCED COMMUNICATIONS Table 3 Other Pins (cont...) Pin Number Symbol I/O 18 MFrSync O 19, O1POS O1NEG 28 IP_FREQ0 I 29 SEC1 I 30 SEC2 I 33 IP_FREQ1 I 34 IP_FREQ2 I 35 O2_FREQ0 I 36 O2_FREQ2 I ...
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ADVANCED COMMUNICATIONS Introduction The ACS8526 is a highly integrated, single-chip solution for protection switching of two SEC inputs from, for example, Master and Slave SETS clock cards sources, for Line Cards in a SONET or SDH Network Element. The ACS8526 ...
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ADVANCED COMMUNICATIONS Input frequencies supported range from 2 kHz to 155.52 MHz. Common E1, DS1, OC-3 and sub-divisions are supported as spot frequencies that the DPLLs will directly lock to. Any input frequency 100 MHz, that is a ...
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ADVANCED COMMUNICATIONS Lock8K Mode Lock8K mode automatically sets the divider parameters to divide the input frequency down to 8 kHz. Lock8K can only be used on the supported spot frequencies. See divn_SEC1 and 2 descriptions (Bit 7 of Reg. 22 ...
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ADVANCED COMMUNICATIONS input phase change, DPLL bandwidth, DPLL frequency limit, and phase detector capture range. The ACS8526 always complies with GR-1244-CORE 3 (max rate of phase change of 81 ns/1.326 ms), for input frequencies at 6.48 MHz or higher, with ...
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ADVANCED COMMUNICATIONS Figure 3 Inactivity and Irregularity Monitoring Inactivities/Irregularities Reference Source Leaky Bucket Response Alarm Leaky Bucket Timing The time taken (in seconds) to raise an inactivity alarm on an SEC that has previously been fully active (Leaky Bucket empty) ...
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ADVANCED COMMUNICATIONS range of output frequencies and levels of jitter performance. However if the device is configured by hardware alone, then the PLLs are configured as shown in Table 7 and 8. Digital Synthesis is used to generate all required ...
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ADVANCED COMMUNICATIONS Figure 4 PLL Block Diagram sts_current_phase DPLL2 PFD and Loop Filter 8 kHz 8 kHz DPLL1 sts_current_phase DPLL1 PFD and Reference Forward Input Loop Filter Feedback Locking Frequency DFS is a technique for generating an output frequency using ...
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ADVANCED COMMUNICATIONS frequencies are listed in Table 12, “APLL2 Frequencies,” on page 24. Similarly to DPLL1, the output of the DPLL2 Forward DFS block is generated using DFS clocked by the 204.8 MHz system clock and will have an inherent ...
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ADVANCED COMMUNICATIONS PFD and Loop Filters The PFD compares the input reference with that of the locking frequency (feedback) giving a phase error which is then filtered by a 100Hz low pass filter, to give the average phase error for ...
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ADVANCED COMMUNICATIONS Damping Factor Programmability The DPLL damping factor is set by default to provide a maximum wander gain peak of around 0.1 dB. Many of the specifications (e.g. GR-1244-CORE [8] G.813 ) specify a wander transfer gain of less ...
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ADVANCED COMMUNICATIONS The characteristics of the loop will be similar to Lock8k mode where again large input phase differences contribute to the loop dynamics. Setting the bit Low only uses a max figure of 360° in the loop and will ...
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ADVANCED COMMUNICATIONS Adjustable gain settings for PD2 (when enabled), for the following feedback cases: • Digital feedback (Reg. 6D Bits [2:0]) • Analog feedback (all frequencies above 8 kHz) (Reg. 6D Bits [6:4]) • Analog 8k (or less) feedback (Reg. ...
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ADVANCED COMMUNICATIONS 4. Refer to Table 13, O1 and O2 Output Frequency Selection, and the column headings in Table 10, Frequency Divider Look-up, to select the appropriate frequency from either of the APLLs on each output as required. Table 6 ...
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ADVANCED COMMUNICATIONS Table 8 Output Reference Source Selection Table Port Output Port Name Technology Output LVDS/PECL O1 (LVDS default) Frequency selection as per Table 9 and Table 13 Output TTL/CMOS O2 FrSync TTL/CMOS FrSync, 8 kHz programmable pulse width and ...
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ADVANCED COMMUNICATIONS Table 9 Output Frequency Selection (cont...) Frequency (MHz, unless stated otherwise) 2.059 (not Output O1) 2.316 2.316 2.731 2.731 2.731 (not Output O1) 2.796 3.088 3.088 3.088 (not Output O1) 3.088 via Digital1 or Digital2 (not Output O1) ...
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ADVANCED COMMUNICATIONS Table 9 Output Frequency Selection (cont...) Frequency (MHz, unless stated otherwise) 8.192 8.192 8.192 8.192 8.192 via Digital1 or Digital2 (not Output O1) 8.192 via Digital1 or Digital2 (not Output O1) 8.235 9.264 9.264 9.264 10.923 11.184 12.288 ...
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ADVANCED COMMUNICATIONS Table 9 Output Frequency Selection (cont...) Frequency (MHz, unless stated otherwise) 18.528 18.528 18.528 19.44 19.44 19.44 21.845 22.368 24.576 24.576 24.576 24.704 24.704 24.704 24.704 25.92 25.92 32.768 32.768 32.768 34.368 37.056 37.056 37.056 38.88 38.88 38.88 ...
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ADVANCED COMMUNICATIONS Table 9 Output Frequency Selection (cont...) Frequency (MHz, unless stated otherwise) 51.84 65.536 (Output O1 only) 68.736 74.112 (Output O1 only) 77.76 77.76 77.76 98.304 (Output O1 only) 98.816 (Output O1 only) 131.07 (Output O1 only) 148.22 (Output ...
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ADVANCED COMMUNICATIONS Table 11 APLL1 Frequencies APLL1 Frequency Synthesis/MUX setting for APLL1 311.04 Normal (digital feedback) 311.04 MHz Normal (analog feedback) 98.304 MHz 12E1 (digital feedback) 131.072 MHz 16E1 (digital feedback) 148.224 MHz 24DS1 (digital feedback) 98.816 MHz 16DS1 (digital ...
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ADVANCED COMMUNICATIONS “Digital” Frequencies Table 13, “O1 and O2 Output Frequency Selection,” lists Digital1 and Digital2 as available for selection. Digital1 is a single frequency selected from the range shown in Table 13 O1 and O2 Output Frequency Selection Output ...
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ADVANCED COMMUNICATIONS Figure 6 Control of 8k Options. 02 Output FrSync at 8 kHz, or Output 01 at 8kHz a) Clock non-inverted, Reg.7A[3: Output FrSync at 8 kHz, or Output 01 at 8kHz b) Pulse non-inverted, Reg.7A[3:2] ...
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ADVANCED COMMUNICATIONS Local Oscillator Clock The Master system clock on the ACS8526 should be provided by an external clock oscillator of frequency 12.800 MHz. Wander on the local oscillator clock will not have a significant effect on the output clock ...
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ADVANCED COMMUNICATIONS Figure 7 Write Access Timing for SERIAL Interface CSB t su2 SCLK su1 SDI R/W SDO Output not driven, pulled low by internal resistor Table 15 Write ...
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ADVANCED COMMUNICATIONS Figure 8 Read Access Timing for SERIAL Interface CLKE = 0; SDO data is clocked out on the rising edge of SCLK CSB t su2 SCLK t su1 SDI R/W ...
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ADVANCED COMMUNICATIONS Register Map Each Register, or register group, is described in the following Register Map (Table 17) and subsequent Register Description Tables. Register Organization The ACS8526 LC/P LITE uses a total of 46 eight-bit registers, identified by a Register ...
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ADVANCED COMMUNICATIONS Table 17 Register Map Register Name RO = Read Only 7 (msb) R/W = Read/Write chip_id (RO chip_revision (RO test_register1 (R/ Phase_alarm (RO) sts_current_DPLL_frequency [7: (RO) [15:8] 0D ...
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ADVANCED COMMUNICATIONS Register Descriptions 00 Address (hex): Register Name chip_id Bit 7 Bit 6 Bit No. Description [7:0] chip_id Least significant byte of the 2-byte device ID. 01 Address (hex): Register Name chip_id Bit 7 Bit 6 Bit No. Description ...
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ADVANCED COMMUNICATIONS 03 Address (hex): Register Name test_register1 Bit 7 Bit 6 phase_alarm disable_180 Bit No. Description 7 phase_alarm (phase alarm (R/O)) Instantaneous result from DPLL1. 6 disable_180 Normally the DPLL will try to lock to the nearest edge (±180°) ...
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ADVANCED COMMUNICATIONS 07 Address (hex): Register Name sts_current_DPLL_frequency [18:16] Bit 7 Bit 6 Bit No. Description [7:3] Not used. [2:0] Bits [18:16] of sts_current_DPLL_frequency When Bit 4 (DPLL1_DPLL2_select) of Reg. 4B (cnfg_registers_source_select the frequency for DPLL1 is reported. ...
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ADVANCED COMMUNICATIONS 0D Address (hex): Register Name sts_current_DPLL_frequency [15:8] Bit 7 Bit 6 Bit No. Description [7:0] Bits [15:8] of sts_current_DPLL_frequency The value in this register is combined with the value in Reg. 0C and Reg represent the ...
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ADVANCED COMMUNICATIONS 22 Address (hex): Register Name cnfg_ref_source_frequency SEC1 Bit 7 Bit 6 divn_SEC<n> lock8k_SEC<n> Bit No. Description 7 divn_SEC<n> This bit selects whether or not input SEC<n> is divided in the programmable pre-divider prior to being input to the ...
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ADVANCED COMMUNICATIONS 34 Address (hex): Register Name cnfg_input_mode Bit 7 Bit 6 XO_edge Bit No. Description [7:6] Not used. 5 XO_edge If the 12.8 MHz oscillator module connected to REFCLK has one edge faster than the other, then for jitter ...
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ADVANCED COMMUNICATIONS 38 Address (hex): Register Name cnfg_dig_outputs_sonsdh Bit 7 Bit 6 dig2_sonsdh dig1_sonsdh Bit No. Description 7 Not used. 6 dig2_sonsdh Selects whether the frequencies generated by the Digital2 frequency generator are SONET derived or SDH. Default value of ...
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ADVANCED COMMUNICATIONS 3A Address (hex): Register Name cnfg_differential_output Bit 7 Bit 6 Bit No. Description [7:2] Not used. [1:0] Output O1_LVDS_PECL Selection of the electrical compatibility of Output O1 between 3 V PECL and 3 V LVDS. 3B Address (hex): ...
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ADVANCED COMMUNICATIONS 3C Address (hex): Register Name cnfg_nominal_frequency [7:0] Bit 7 Bit 6 Bit No. Description [7:0] cnfg_nominal_frequency_value[7:0]. 3D Address (hex): Register Name cnfg_nominal_frequency [15:8] Bit 7 Bit 6 Bit No. Description [7:0] cnfg_nominal_frequency_value[15:8] This register is used in conjunction ...
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ADVANCED COMMUNICATIONS 41 Address (hex): Register Name cnfg_DPLL_freq_limit [7:0] Bit 7 Bit 6 Bit No. Description [7:0] Bits [7:0] of cnfg_DPLL_freq_limit This register defines the extent of frequency offset to which DPLL1 will track a source before limiting- i.e. it ...
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ADVANCED COMMUNICATIONS 46 Address (hex): Register Name cnfg_freq_divn [7:0]. Bit 7 Bit 6 Bit No. Description [7:0] divn_value[7:0]. 47 Address (hex): Register Name cnfg_freq_divn [13:8] Bit 7 Bit 6 Bit No. Description [7:6] Not used. [5:0] divn_value[13:8] This register, in ...
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ADVANCED COMMUNICATIONS 4B (cont...) Address (hex): Register Name cnfg_registers_source_select Bit 7 Bit 6 Bit No. Description 4 DPLL1_DPLL2_select Bit to select between many of the registers associated with DPLL1 or DPLL2 e.g. frequency registers. [3:0] Not used. 4D Address (hex): ...
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ADVANCED COMMUNICATIONS 50 Address (hex): Register Name cnfg_upper_threshold Bit 7 Bit 6 upper_threshold_value (Activity alarm, Leaky Bucket - set threshold) Bit No. Description [7:0] upper_threshold_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects ...
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ADVANCED COMMUNICATIONS 52 Address (hex): Register Name cnfg_bucket_size Bit 7 Bit 6 Bit No. Description [7:0] bucket_size_value The Leaky Bucket operates on a 128 ms cycle. If, during a cycle, it detects that an input has either failed or has ...
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ADVANCED COMMUNICATIONS 61 Address (hex): Register Name cnfg_output_frequency (Output O2) Bit 7 Bit 6 Bit No. Description [7:4] Not used. [3:0] output_freq_O2 Configuration of the output frequency available at Output O2. Many of the frequencies available are dependent on the ...
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ADVANCED COMMUNICATIONS 62 Address (hex): Register Name cnfg_output_frequency (Output O1) Bit 7 Bit 6 output_freq_O1 Bit No. Description [7:4] output_freq_O1 Configuration of the output frequency available at Output O1. Many of the frequencies available are dependent on the frequencies of ...
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ADVANCED COMMUNICATIONS 63 (cont...) Address (hex): Register Name cnfg_output_frequency (MFrSync/FrSync) Bit 7 Bit 6 MFrSync_en FrSync_en Bit No. Description 6 FrSync_en Register bit to enable the 8 kHz Sync output (FrSync). [5:0] Not used. 64 Address (hex): Register Name cnfg_DPLL2_frequency ...
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ADVANCED COMMUNICATIONS 65 Address (hex): Register Name cnfg_DPLL1_frequency Bit 7 Bit 6 APLL2_for_ DPLL1_E1/DS1 Bit No. Description 7 Not used. 6 APLL2_for_DPLL1_E1/DS1 Register bit to control MUX2 which selects whether the APLL2 takes its input from DPLL2 or DPLL1. If ...
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ADVANCED COMMUNICATIONS 66 (cont...) Address (hex): Register Name cnfg_DPLL2_bw Bit 7 Bit 6 Bit No. Description [1:0] DPLL2_bandwidth Register to configure the bandwidth of DPLL2. 67 Address (hex): Register Name cnfg_DPLL1_locked_bw Bit 7 Bit 6 Bit No. Description [7:2] Not ...
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ADVANCED COMMUNICATIONS 69 (cont...) Address (hex): Register Name cnfg_DPLL1_acq_bw Bit 7 Bit 6 Bit No. Description [3:0] DPLL1_acquisition_bandwidth Register to configure the bandwidth of DPLL1 when acquiring phase lock on an input reference. Reg. 3B Bit 7 is used to ...
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ADVANCED COMMUNICATIONS 6A (cont...) Address (hex): Register Name cnfg_DPLL2_damping Bit 7 Bit 6 DPLL2_PD2_gain_alog Bit No. Description [2:0] DPLL2_damping Register to configure the damping factor of DPLL2. The bit values correspond to different damping factors, depending on the bandwidth selected. ...
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ADVANCED COMMUNICATIONS 6B (cont...) Address (hex): Register Name cnfg_DPLL1_damping Bit 7 Bit 6 DPLL1_PD2_gain_alog_8k Bit No. Description [2:0] DPLL1_damping Register to configure the damping factor of DPLL1. The bit values correspond to different damping factors, depending on the bandwidth selected. ...
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ADVANCED COMMUNICATIONS 6D Address (hex): Register Name cnfg_DPLL1_PD2_gain Bit 7 Bit 6 DPLL1_PD2_ DPLL1_PD2_gain_alog gain_enable Bit No. Description 7 DPLL1_PD2_gain_enable [6:4] DPLL1_PD2_gain_alog Register to control the gain of Phase Detector 2 when locking to a reference, higher than 8 kHz, ...
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ADVANCED COMMUNICATIONS 73 Address (hex): Register Name cnfg_phase_loss_fine_limit Bit 7 Bit 6 fine_limit_en noact_ph_loss narrow_en Bit No. Description 7 fine_limit_en Register bit to enable the phase_loss_fine_limit Bits [2:0]. When disabled, phase lock/loss is determined by the other means within the ...
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ADVANCED COMMUNICATIONS 74 Address (hex): Register Name cnfg_phase_loss_coarse_limit Bit 7 Bit 6 coarse_lim_ wide_range_en multi_ph_resp phaseloss_en Bit No. Description 7 coarse_lim_phaseloss_en Register bit to enable the coarse phase detector, whose range is determined by phase_loss_coarse_limit Bits [3:0]. This register sets ...
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ADVANCED COMMUNICATIONS 74 (cont...) Address (hex): Register Name cnfg_phase_loss_coarse_limit Bit 7 Bit 6 coarse_lim_ wide_range_en multi_ph_resp phaseloss_en Bit No. Description [3:0] phase_loss_coarse_limit Sets the range of the coarse phase loss detector and the coarse phase detector. When locking to a ...
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ADVANCED COMMUNICATIONS 7A Address (hex): Register Name cnfg_sync_pulses Bit 7 Bit 6 2k_8k_from_ DPLL2 Bit No. Description 7 2k_8k_from_DPLL2 Register to select the source (DPLL1 or DPLL2) for the 2 kHz and 8 kHz outputs available from O1 and O2. ...
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ADVANCED COMMUNICATIONS 7D Address (hex): Register Name cnfg_LOS_alarm Bit 7 Bit 6 Bit No. Description [7:3] Not used. 2 LOS_GPO_en (General Purpose Output). If the LOS_ALARM output pin is not required, then setting this bit will allow the pin to ...
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ADVANCED COMMUNICATIONS 7E Address (hex): Register Name cnfg_protection Bit 7 Bit 6 Bit No. Description [7:0] protection_value This register can be used to ensure that the software writes a specific value to this register, before being able to modify any ...
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ADVANCED COMMUNICATIONS Electrical Specifications JTAG The JTAG connections on the ACS8526 allow a full boundary scan to be made. The JTAG implementation is [4] fully compliant to IEEE 1149.1 , with the following minor exceptions, and the user should refer ...
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ADVANCED COMMUNICATIONS Maximum Ratings Important Note: The Absolute Maximum Ratings, Table 19, are stress ratings only, and functional operation of the device at conditions other than those indicated in the Operating Conditions sections of this specification are not implied. Exposure ...
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ADVANCED COMMUNICATIONS Table 22 DC Characteristics: TTL Input Port with Internal Pull-up Across all operating conditions, unless otherwise stated Parameter V High IN V Low IN Pull-up Resistor Input Current Table 23 DC Characteristics: TTL Input Port with Internal Pull-down ...
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ADVANCED COMMUNICATIONS Figure 10 Recommended Line Termination for PECL Output Port Table 26 DC Characteristics: LVDS Output Port Across all operating conditions, unless otherwise stated Parameter LVDS Output High Voltage (Note (i)) LVDS Output Low Voltage (Note (i)) LVDS Differential ...
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ADVANCED COMMUNICATIONS Jitter Performance Output jitter generation measured over 60 second interval, UI p-p max measured using C-MAC E2747 12.8 MHz TCXO on ICT Flexacom tester. Table 27 Output Jitter Generation bandwidth and 8 kHz Input Specification ...
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ADVANCED COMMUNICATIONS Table 27 Output Jitter Generation bandwidth and 8 kHz Input (cont...) Specification [12] [9] GR-499-CORE & G824 for 1.544 MHz [12] [9] GR-499-CORE & G824 for 1.544 MHz [13] GR-1244-CORE for 1.544 MHz Note...This table ...
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ADVANCED COMMUNICATIONS Input/Output Timing Figure 12 Input/Output Timing (Typical Conditions) Input/Output 8 kHz input 8 kHz output 6.48 MHz input 6.48 MHz output 19.44 MHz input 19.44 MHz output 25.92 MHz input 25.92 MHz output 38.88 MHz input 38.88 MHz ...
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ADVANCED COMMUNICATIONS Package Information Figure 13 LQFP Package Seating plane A1 Notes 1 The top package body may be smaller than the bottom package body by as much as 0.15 mm ...
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ADVANCED COMMUNICATIONS Thermal Conditions The device is rated for full temperature range when this package is used with a 4 layer or more PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum operating temperature ...
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ADVANCED COMMUNICATIONS Application Information Figure 15 Simplified Application Schematic term_connect An example setup where input and output clocks are hard wired to accept 19.44MHz on SEC1 and SEC2. The outputs are configured as: O1 -> 155.52MHz O2 ...
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ADVANCED COMMUNICATIONS Abbreviations APLL Analogue Phase Locked Loop BITS Building Integrated Timing Supply DFS Digital Frequency Synthesis DPLL Digital Phase Locked Loop DS1 1544 kbit/s interface rate DTO Discrete Time Oscillator E1 2048 kbit/s interface rate I/O Input - Output ...
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ADVANCED COMMUNICATIONS Trademark Acknowledgements Semtech and the Semtech S logo are registered trademarks of Semtech Corporation. ACCUNET ® registered trademark of AT & T. C-MAC is a registered trademark of C-MAC MicroTechnology - a division of Solectron Corporation. ...
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ADVANCED COMMUNICATIONS Revision Status/History The Revision Status of the datasheet, as shown in the center of the datasheet header bar, may be DRAFT, PRELIMINARY, or FINAL, and refers to the status of the Device (not the datasheet) within the design ...
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ADVANCED COMMUNICATIONS Ordering Information Table 30 Parts List Part Number ACS8526 ACS8526T Lead (Pb)-free package version of ACS8526; RoHS and WEEE compliant. Disclaimers Life support- This product is not designed or intended for use in life support equipment, devices or ...