la1862m Sanyo Semiconductor Corporation, la1862m Datasheet - Page 15

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la1862m

Manufacturer Part Number
la1862m
Description
Single-chip Tuner System For Car Stereo
Manufacturer
Sanyo Semiconductor Corporation
Datasheet

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4.
Noise Canceller Block
1.
2.
3.
4.
Noise canceller input waveform
5.
The following figure illustrates one possible circuit design using both the IF count buffer and the SD output circuit.
The resistor and capacitor connected to pin 6 determine
the noise canceller sensitivity.
The resistor and capacitor connected to pin 7 determine
the noise AGC.
Pin 9 is the gate trigger output. The resistor and capacitor
connected to pin 9 determine the length of time that the
gate is open.
The resistor and capacitor connected to pins 10 and 11 are
for holding the input signal level when the noise canceller
gate operates. The storage time depends on the time that
the gate is open. The time constant for the RC circuit on
pins 10 and 11 must, therefore, be such that the output
retention signal level does not drop during this interval.
Pin 26 is the noise canceller input. An appropriate input level is 250 mVrms for 100% dev and fm = 1 kHz. Excessive input
can exceed the noise canceller dynamic range, increasing the THD. Insufficient input, on the other hand, lowers the
signal-to-noise ratio and reduces pilot lamp sensitivity.
IF count buffer output
LA1862M
Apply 5 V for seek
SD output
Noise canceller output waveform
Output retention
(storage)
No. 4092- 15/27

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