mx27c1610 Macronix International Co., mx27c1610 Datasheet
mx27c1610
Related parts for mx27c1610
mx27c1610 Summary of contents
Page 1
... Fast access time: 100/120 ns • Totally static operation GENERAL DESCRIPTION The MX27C1610 is a 16M-bit, One Time Programmable Read Only Memory organized and has a static standby mode, and features fast programming. For programming outside from the sys- tem, existing EPROM programmers may be used ...
Page 2
... DOUT NOTE : FUNCTIONAL DESCRIPTION READ MODE The MX27C1610 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection ...
Page 3
... A1= VIL, other address lines not specified are at "X" states 4. See DC Programming Characteristics for VPP voltages. 5. BYTE/VPP is intended for operation under DC Voltage conditions only. VPP=10V± 0.5V for write operation P/N:PM0593 MX27C1610 WRITE OPERATIONS Commands are written to the COMMAND INTERFACE REGISTER (CIR) using standard microprocessor write timings ...
Page 4
... A0 from VIL to VIH. All addresses are don't cares except A0 and A1. The manufacturer and device codes may also be read via the command register, for instances when the MX27C1610 is programmed in a system without access to high voltage on the A9 pin ...
Page 5
... Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. The MX27C1610 is accessed when CE and OE are low the data stored at the memory location determined by the address pins is asserted on the outputs. The out- puts are put in the high impedance state whenever high ...
Page 6
... However, the WSM can only clear bit 7 but can not clear bit 4. If Program fail status bit is detected, the Status Register is not cleared until the "Clear Status Register command" is issued. The MX27C1610 automatically out- puts Status Register data when read after Page Pro- gram or Read Status Command write cycle. The inter- nal state machine is set for reading array data upon device power-up ...
Page 7
... WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 10ns (typical will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one VIL,CE = VIH. To initiate a write cycle CE must be a logical zero while logical one, and BYTE/VPP=10V. P/N:PM0593 MX27C1610 NOTES 1,2 ...
Page 8
... AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are < 10ns. P/N:PM0593 MIN. TYP. MAX 1.2K ohm 2.0V 2.0V TEST POINTS 0.8V 0.8V INPUT 8 MX27C1610 UNIT CONDITIONS pF VIN = 0V pF VPP=0V pF VOUT = 0V 1.6K ohm +5V DIODES = IN3064 OR EQUIVALENT OUTPUT REV. 1.4, NOV. 19, 2002 ...
Page 9
... VCC+0.3 V 0.45 2.4 9 MX27C1610 UNITS TEST CONDITIONS uA VCC = VCC Max VIN = VCC or GND uA VCC = VCC Max VIN = VCC or GND uA VCC = VCC Max CE = VCC±0.2V mA VCC = VCC Max CE = VIH mA VCC = VCC Max CMOS GND± 0.2V BYTE/VPP = GND±0.2V or VCC± ...
Page 10
... TEST CONDITIONS: • Input pulse levels: 0.45V/2.4V • Input rise and fall times: 10ns • Output load: 1TTL gate+100pF(Including scope and jig) • Reference levels for measuring timing: 0.8V, 2.0V P/N:PM0593 MX27C1610 27C1610-10 27C1610-12 MIN. MAX. MIN. MAX. 100 120 100 120 50 50 ...
Page 11
... BYTE/VPP pin should be either static high(word mode) or static low(byte mode); dynamic switching of BYTE/VPP pin is not recommended. P/N:PM0593 Device and Outputs Enabled address selection ADDRESSES STABLE tOE tCE tACC 11 MX27C1610 Standby Power-down Data valid Vcc tDF tOH HIGH Z Data out valid REV. 1.4, NOV. 19, 2002 ...
Page 12
... VIH ADDRESSES VIL VIH VIL CE VIH VIL OE VIH VIL BYTE VOH HIGH Z DATA(Q0-Q7) VOL VOH HIGH Z DATA(Q8-Q15) VOL P/N:PM0593 MX27C1610 ADDRESSES STABLE tBACC tOE tCE Data Output tACC tBHZ Data Output 12 tDF tOH HIGH Z Data Output HIGH Z REV. 1.4, NOV. 19, 2002 ...
Page 13
... Word Address Load Cycle tBAL Word Address Load Time tSRA Status Register Access Time tCESR CE Setup before S.R. Read tVCS VCC Setup Time tRAW Read Operation Set Up Time After Write P/N:PM0593 MX27C1610 27C1610-10 27C1610-12 MIN. MAX. MIN. 100 120 ...
Page 14
... ADDRESSES HIGH Z DATA (Q0~Q15) VCC tVCS 10V VIH BYTE/VPP VIL NOTE: 1.BYTE/VPP pin should be static at 10V+0.5V during Write operation. 2.BYTE/VPP pin should be static at TTL, or CMOS level, during Read operation. P/N:PM0593 tCS tAH VALID tDS DIN 14 MX27C1610 tDH REV. 1.4, NOV. 19, 2002 ...
Page 15
... OE going low to "read mode", BYTE/VPP must from VH(10V) to VIH or VIL P/N:PM0593 Word offset AAH 55H Address Page Address 2AH 55H Page Address tBALC Write 55H A0H Data 15 MX27C1610 Last Word offset Address tBAL tCES tRAW VIH VIL tSRA Last Write SRD Data REV. 1.4, NOV. 19, 2002 ...
Page 16
... Byte Program Time LATCHUP CHARACTERISTICS Input Voltage with respect to GND on all pins except I/O pins Input Voltage with respect to GND on all I/O pins Current Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. P/N:PM0593 MX27C1610 LIMITS MIN. TYP. MAX. UNITS 0.9 ...
Page 17
... PACKAGE INFORMATION P/N:PM0593 MX27C1610 17 REV. 1.4, NOV. 19, 2002 ...
Page 18
... Revision History Revision No. Description 1.3 Changed title from "Advanced Information" to "Preliminary" 1.4 To modify package information P/N:PM0593 MX27C1610 Page P1 P17 18 Date APR/26/2000 NOV/19/2002 REV. 1.4, NOV. 19, 2002 ...
Page 19
... TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 ACRONIX MERICA, NC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com C L O., TD. MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 19 MX27C1610 ...