lvch16260a Integrated Device Technology, lvch16260a Datasheet - Page 6

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lvch16260a

Manufacturer Part Number
lvch16260a
Description
3.3v Cmos 12-bit Tri-port Bus Exchanger With 5 Volt Tolerant I/o And Bus-hold
Manufacturer
Integrated Device Technology
Datasheet
DEFINITIONS:
C
R
NOTE:
1. Pulse Generator for All Pulses: Rate
2. Pulse Generator for All Pulses: Rate
NOTES:
1. For t
2. For t
IDT74LVCH16260A
3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5 VOLT I/O
Symbol
L
T
Generator
V
= Load capacitance: includes jig and probe capacitance.
= Termination resistance: should be equal to Z
V
V
LOAD
V
V
C
Pulse
HZ
LZ
Generator.
IH
T
L
OUTPUT 2
OUTPUT 1
SK
SK
INPUT
(1, 2)
(o) OUTPUT1 and OUTPUT2 are any two outputs.
(b) OUTPUT1 and OUTPUT2 are in the same bank.
V
All Other tests
Disable High
CC
Disable Low
Enable High
Enable Low
Open Drain
(1)
Test
= 3.3V ±0.3V
V
300
300
IN
2.7
1.5
50
6
t
SK
(x)
R
= t
T
t
D.U.T.
PLH1
V
PLH2
CC
t
PLH2
V
CC
-
t
(1)
SK
t
300
300
PLH1
2.7
1.5
50
V
6
= 2.7V
(x)
OUT
10MHz; t
10MHz; t
or
t
PHL1
t
C
PHL2
t
PHL2
L
V
OUT
CC
F
F
t
Switch
SK
-
(2)
V
Open
GND
of the Pulse
t
LOAD
P HL1
500
2.5ns; t
2ns; t
2 x Vcc
500
= 2.5V ±0.2V Unit
V
(x)
Vcc
CC
150
150
30
LVC Link
/ 2
LVC Link
R
0V
V
V
V
R
V
V
V
V
V
T
T
OL
T
OL
IH
OH
OH
2ns.
V
Open
GND
2.5ns.
LOAD
LVC Link
LVC Link
mV
mV
pF
V
V
V
6
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
ASYNCHRONOUS
SYNCHRONOUS
Disable-HIGH.
INPUT TRANSITION
INPUT TRANSITION
OPPOSITE PHASE
NORMALLY
NORMALLY
HIGH-LOW -HIGH
CONTROL
CONTROL
LOW -HIGH-LOW
CONTROL
SAME PHASE
OUTPUT
OUTPUT
TIM ING
INPUT
INPUT
DATA
INPUT
EXTENDED COMMERCIAL TEMPERATURE RANGE
HIGH
OUTPUT
LOW
PULSE
PULSE
CLO SED
SW ITCH
SW ITCH
ENABLE
OPEN
t
t
PZH
PZL
t
t
PLH
PLH
t
S U
t
SU
V
0V
V
V
T
T
LOAD/2
t
W
t
R EM
t
t
H
PHZ
t
t
DISABLE
PHL
PHL
t
H
t
PLZ
LVC Link
LVC Link
V
LVC Link
V
T
T
LVC Link
V
V
0V
V
V
V
V
V
0V
0V
V
V
0V
V
V
V
V
V
IH
OH
T
T
OL
IH
T
T
IH
LOAD/2
LZ
OH
HZ
OL
0V
0V
0V
0V
V
V
V
V
V
V
V
V
T
T
T
T
IH
IH
IH
IH

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