em78p613 ELAN Microelectronics Corp, em78p613 Datasheet - Page 40

• Manufacturer Part Number: em78p613
• Description: Universal Serial Bus Series Microcontroller
• Manufacturer: ELAN Microelectronics Corp

EM78P613
Universal Serial Bus Series Microcontroller
B Instruction Set
36 •
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. All instructions are executed within one single instruction cycle
(consisting of two oscillator periods), unless the program counter is changed by
(a) Executing the instruction "MOV R2, A", "ADD R2,A", "TBL", or any other
(b) Executing CALL, RET, RETI, RETL, JMP, Conditional skip (JBS, JBC, JZ, JZA,
Under these cases, the execution takes two instruction cycles.
In addition, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction
Legend:
R = Register designator that specifies which one of the 64 registers (including operation and
b = Bit field designator that selects the value for the bit located in the register R and which affects
k = 8 or 10-bit constant or literal value
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0010
0 0000 0000 0011
0 0000 0000 0100
0 0000 0000 rrrr
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
0 0000 0001 0011
0 0000 0001 0100
0 0000 0001 rrrr
0 0000 0010 0000
0 0000 01rr rrrr
0 0000 1000 0000
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
Binary Instruction
general purpose registers) is to be utilized by the instruction.
Bits 6 and 7 in R4 determine the selected register bank.
the operation.
instructions that write to R2 (e.g. "SUB R2,A", "BS R2,6", "CLR R2", etc.).
DJZ, DJZA) which were tested to be true.
can operate on any I/O register.
0000
0001
0002
0003
0004
000r
0010
0011
0012
0013
0014
001r
0020
00rr
0080
00rr
01rr
01rr
Hex
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
RETI
CONTR
IOR R
TBL
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
Mnemonic
(This specification is subject to change without further notice)
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC,
Enable Interrupt
CONT → A
IOCR → A
R2+A → R2,
Bits 8~9 of R2 unchanged
A → R
0 → A
0 → R
R-A → A
R-A → R
Product Specification (V1.0) 01.09.2009
Operation
Status Affected
A, R3, R4,R8.7
Z, C, DC
Z, C, DC
Z, C, DC
None
None
None
None
None
None
None
None
None
T, P
T, P
C
Z
Z
1
1
−