ATSAM3U_10 ATMEL [ATMEL Corporation], ATSAM3U_10 Datasheet

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ATSAM3U_10

Manufacturer Part Number
ATSAM3U_10
Description
AT91ARM Cortex M3-based Microcontrollers
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
Features
Core
Memories
System
Low Power Modes
Peripherals
I/O
Packages
– ARM
– Memory Protection Unit (MPU)
– Thumb
– From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,
– From 16 to 48 Kbytes embedded SRAM with dual banks
– 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines
– Static Memory Controller (SMC): SRAM, NOR, NAND support. NAND Flash
– Embedded voltage regulator for single supply operation
– POR, BOD and Watchdog for safe reset
– Quartz or resonator oscillators: 3 to 20 MHz main and optional low power 32.768
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz Default
– Slow Clock Internal RC oscillator as permanent clock for device clock in low power
– One PLL for device clock and one dedicated PLL for USB 2.0 High Speed Device
– Up to 17 peripheral DMA (PDC) channels and 4-channel central DMA
– Sleep and Backup modes, down to 2.5 µA in Backup mode
– Backup domain: VDDBU pin, RTC, 32 backup registers
– Ultra low power RTC: 0.6 µA
– USB 2.0 Device: 480 Mbps, 4-kbyte FIFO, up to 7 bidirectional Endpoints,
– Up to 4 USARTs (ISO7816, IrDA
– Up to 2 TWI (I2C compatible), 1 SPI, 1 SSC (I2S), 1 HSMCI (SDIO/SD/MMC)
– 3-Channel 16-bit Timer/Counter (TC) for capture, compare and PWM
– 4-channel 16-bit PWM (PWMC)
– 32-bit Real Time Timer (RTT) and RTC with calendar and alarm features
– 8-channel 12-bit 1MSPS ADC with differential input mode and programmable gain
– Up to 96 I/O lines with external interrupt capability (edge or level sensitivity),
– Three 32-bit Parallel Input/Outputs (PIO)
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm
– 100-ball LFBGA, 9 x 9 mm, pitch 0.8 mm
– 144-lead LQFP, 20 x 20 mm, pitch 0.5 mm
– 144-ball LFBGA, 10 x 10 mm, pitch 0.8 mm
dual bank
controller with 4 Kbytes RAM buffer and ECC
kHz for RTC or device clock.
Frequency for fast device startup
mode
dedicated DMA
UART
stage, 8-channel 10-bit ADC
debouncing, glitch filtering and on-die Series Resistor Termination
®
Cortex
®
-2 instruction set
®
-M3 revision 2.0 running at up to 96 MHz
®
, Flow Control, SPI, Manchester support) and one
AT91ARM
Cortex M3-based
Microcontrollers
ATSAM3U Series
Preliminary
Summary
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
6430CS–ATARM–09-Apr-10

Related parts for ATSAM3U_10

ATSAM3U_10 Summary of contents

Page 1

Features • Core ® ® – ARM Cortex -M3 revision 2.0 running MHz – Memory Protection Unit (MPU) ® – Thumb -2 instruction set • Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide ...

Page 2

SAM3U Description Atmel's SAM3U series is a member of a family of Flash microcontrollers based on the high per- formance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 96 MHz and features up to 256 ...

Page 3

SAM3U Block Diagram Figure 2-1. 144-pin SAM3U4/2/1E Block Diagram MASTER SLAVE System Controller JTAG & Serial Wire TST PCK0 -PCK2 In-Circuit Emulator PLLA SysTick Counter UPLL Cortex-M3 Processor PMC Fmax 96 MHz OSC XIN 3-20 M XOUT MPU RC ...

Page 4

Figure 2-2. 100-pin SAM3U4/2/1C Block Diagram MASTER SLAVE System Controller JTAG & Serial Wire TST PCK0 -PCK2 In-Circuit Emulator PLLA SysTick Counter UPLL Cortex-M3 Processor PMC Fmax 96 MHz OSC XIN XOUT 3-20 M MPU RC Osc. I/D 12/8/4 M ...

Page 5

Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function VDDIO Peripherals I/O Lines Power Supply VDDIN Voltage Regulator Input VDDOUT Voltage Regulator Output VDDUTMII USB UTMI+ Interface Power Supply GNDUTMII USB UTMI+ Interface Ground VDDBU Backup ...

Page 6

Table 3-1. Signal Description List (Continued) Signal Name Function ERASE Flash and NVM Configuration Bits Erase Command NRST Microcontroller Reset NRSTB Asynchronous Microcontroller Reset TST Test Select URXD UART Receive Data UTXD UART Transmit Data PA0 - PA31 Parallel IO ...

Page 7

Table 3-1. Signal Description List (Continued) Signal Name Function CK Multimedia Card Clock CDA Multimedia Card Slot A Command DA0 - DA7 Multimedia Card Slot A Data Universal Synchronous Asynchronous Receiver Transmitter - USARTx SCKx USARTx Serial Clock TXDx USARTx ...

Page 8

Table 3-1. Signal Description List (Continued) Signal Name Function TWDx TWIx Two-wire Serial Data TWCKx TWIx Two-wire Serial Clock AD12Bx Analog Inputs AD12BTRG ADC Trigger AD12BVREF ADC Reference ADx Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN2 Programming Enabling ...

Page 9

Package and Pinout The SAM3U4/2/1E is available in 144-lead LQFP and 144-ball LFBGA packages. The SAM3U4/2/1C is available in 100-lead LQFP and 100-ball LFBGA packages. 4.1 SAM3U4/2/1E Package and Pinout 4.1.1 144-ball LFBGA Package Outline The 144-Ball LFBGA package ...

Page 10

LQFP Pinout Table 4-1. 144-pin SAM3U4/2/1E Pinout 1 TDI 37 2 VDDOUT 38 3 VDDIN 39 4 TDO/TRACESWO 40 5 PB31 41 6 PB30 42 7 TMS/SWDIO 43 8 PB29 44 9 TCK/SWCLK 45 10 PB28 46 11 ...

Page 11

LFBGA Pinout Table 4-2. 144-ball SAM3U4/2/1E Pinout A1 VBG A2 VDDUTMI A3 PB9 A4 PB10 A5 PB19 A6 PC21 A7 PB26 A8 TCK/SWCLK A9 PB30 A10 TDO/TRACESWO A11 XIN32 A12 XOUT32 B1 VDDCORE B2 GNDUTMI B3 XOUT B4 ...

Page 12

SAM3U4/2/1C Package and Pinout 4.2.1 100-lead LQFP Package Outline Figure 4-3. 4.2.2 100-ball LFBGA Package Outline Figure 4-4. SAM3U Series 12 Orientation of the 100-lead LQFP Package 75 76 100 1 Orientation of the 100-ball LFBGA Package TOP VIEW ...

Page 13

LQFP Pinout Table 4-3. 100-pin SAM3U4/2/1C1 Pinout 1 VDDANA 2 ADVREF 3 GNDANA 4 AD12BVREF 5 PA22/PGMD14 6 PA30 7 PB3 8 PB4 9 VDDCORE 10 PA13/PGMD5 11 PA14/PGMD6 12 PA15/PGMD7 13 PA16/PGMD8 14 PA17/PGMD9 15 PB16 16 ...

Page 14

LFBGA Pinout Table 4-4. 100-ball SAM3U4/2/1C Pinout A1 VBG C6 A2 XIN C7 A3 XOUT C8 A4 PB17 C9 A5 PB21 C10 A6 PB23 D1 A7 TCK/SWCLK D2 A8 VDDIN D3 A9 VDDOUT D4 A10 XIN32 D5 B1 ...

Page 15

Power Considerations 5.1 Power Supplies The SAM3U product has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V to 1.95V. • VDDIO pins: Power the Peripherals ...

Page 16

Figure 5-1. Note: SAM3U Series 16 Single Supply Main Supply (1.8V-3.6V) Restrictions With Main Supply < 2.0 V, USB and ADC are not usable. With Main Supply ≥ 2.4V and < 3V, USB is not usable. With Main Supply ≥ ...

Page 17

Figure 5-2. Note: 6430CS–ATARM–09-Apr-10 Core Externally Supplied Main Supply (1.62V-3.6V) VDDCORE Supply (1.62V-1.95V) Restrictions With Main Supply < 2.0 V, USB and ADC are not usable. With Main Supply ≥ 2.4V and < 3V, USB is not usable. With Main ...

Page 18

Figure 5-3. Note: SAM3U Series 18 Backup Batteries Used Backup Batteries VDDBU Main Supply (1.62V-3.6V) Restrictions With Main Supply < 2.0 V, USB and ADC are not usable. With Main Supply ≥ 2.4V and < 3V, USB is not usable. ...

Page 19

Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency and to ...

Page 20

Entering Wait Mode: • Select the 4/8/12 MHz Fast RC Oscillator as Main Clock • Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR) • Execute the Wait-For-Event (WFE) instruction of the processor Note: 5.5.3 Sleep Mode ...

Page 21

Low Power Mode Summary Table The modes detailed above are the main low power modes. Each part can be set off sep- arately and wake up sources can be individually configured. of the configurations of the ...

Page 22

Wake-up Sources The wake-up events allow the device to exit backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply. Figure 5-4. Wake-up Source SMEN sm_int RTCEN rtc_alarm ...

Page 23

Fast Start-Up The SAM3U allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs. ...

Page 24

Input/Output Lines The SAM3U has different kinds of input/output (I/O) lines, such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functions thanks to multiplexing capabilities of the PIO controllers. The same GPIO line can be ...

Page 25

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left uncon- nected for normal operations. ...

Page 26

Even in all low power modes, asserting the pin will automatically start-up the chip and erase the Flash. 7. Processor and Architecture 7.1 ARM Cortex-M3 Processor • Version 2.0 • Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit ...

Page 27

Matrix Slaves The Bus Matrix of the SAM3U manages 10 slaves. Each slave has its own arbiter, allowing a dif- ferent arbitration per slave. Table 7-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave ...

Page 28

DMA Controller • Acting as one Matrix Master • Embeds 4 channels: – 3 channels with 8 bytes/FIFO for Channel Buffering – 1 channel with 32 bytes/FIFO for Channel Buffering • Linked List support with Status Write Back operation ...

Page 29

The Peripheral DMA Controller handles transfer requests from the channel according to the fol- lowing priorities (Low to High priorities): Table 7-5. Instance name UART USART3 USART2 USART1 USART0 UART USART3 USART2 USART1 USART0 ADC12B 7.8 Debug and Test Features ...

Page 30

Product Mapping Figure 8-1. SAM3U Memory Mapping Code 0x00000000 Boot Memory 0x00080000 Internal Flash 0 0x00100000 Internal Flash 1 0x00180000 Internal ROM 0x00200000 Reserved 0x1FFFFFFF Internal SRAM 0x20000000 SRAM0 1 MByte 0x20080000 bit band region SRAM1 0x20100000 NFC (SRAM) ...

Page 31

Memories The embedded and external memories are described below. 9.1 Embedded Memories 9.1.1 Internal SRAM The SAM3U4 (256 KBytes internal Flash version) embeds a total of 48 Kbytes high-speed SRAM (32 Kbytes SRAM0 and 16 Kbytes SRAM1). The SAM3U2 ...

Page 32

The user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the ...

Page 33

Calibration Bits NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the cal- ibration bits. 9.1.3.7 ...

Page 34

A general purpose NVM (GPNVM1) bit is used to boot either on the ROM (default) or from the Flash. The GPNVM bit can be cleared or set respectively through the commands “Clear General-pur- pose NVM Bit” and “Set General-purpose NVM ...

Page 35

Supports 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte 6430CS–ATARM–09-Apr-10 pages SAM3U Series 35 ...

Page 36

System Controller The System Controller is a set of peripherals, which allow handling of key elements of the sys- tem, such as power, resets, clocks, time, interrupts, watchdog, etc... The System Controller User Interface also embeds the registers used ...

Page 37

Figure 10-1. System Controller Block Diagram VDDBU FWUP SHDN NRSTB Zero-Power Power-on Reset General Purpose Backup Registers SLCK RTC SLCK RTT osc32k_xtal_en XIN32 Xtal 32 kHz Oscillator XOUT32 Embedded 32 kHz RC osc32k_rc_en Oscillator Backup Power Supply vddcore_nreset NRST FSTT0 ...

Page 38

System Controller and Peripheral Mapping Please refer to All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM3U embeds three features to monitor, ...

Page 39

The Slow Clock generator is based kHz crystal oscillator and an embedded 32 kHz RC oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal oscillator and select it as the ...

Page 40

Power Management Controller The Power Management Controller provides all the clock signals to the system. It provides: • the Processor Clock HCLK • the Free running processor clock FCLK • the Cortex SysTick external clock • the Master Clock ...

Page 41

Watchdog Timer • 16-bit key-protected once-only Programmable Counter • Windowed, prevents the processor dead-lock on the watchdog access 10.8 SysTick Timer • 24-bit down counter • Self-reload capability • Flexible system timer 10.9 Real-time Timer ...

Page 42

Chip Identification • Chip Identifier (CHIPID) registers permit recognition of the device and its revision. Table 10-1. Chip Name SAM3U4C (Rev A) SAM3U2C (Rev A) SAM3U1C (Rev A) SAM3U4E (Rev A) SAM3U2E (Rev A) SAM3U1E (Rev A) • JTAG ...

Page 43

PIO Controllers • 3 PIO Controllers, PIOA, PIOB, and PIOC, controlling a maximum of 96 I/O Lines • Each PIO Controller controls programmable I/O Lines – PIOA has 32 I/O Lines – PIOB has 32 I/O ...

Page 44

Peripherals 11.1 Peripheral Identifiers Table 11-1 the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Note that some Peripherals are always clocked. Please ...

Page 45

Peripheral Signal Multiplexing on I/O Lines The SAM3U features 3 PIO controllers, PIOA, PIOB and PIOC that multiplex the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to ...

Page 46

PIO Controller A Multiplexing Table 11-2. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A PA0 TIOB0 PA1 TIOA0 PA2 TCLK0 PA3 MCCK PA4 MCCDA PA5 MCDA0 PA6 MCDA1 PA7 MCDA2 PA8 MCDA3 PA9 TWD0 PA10 TWCK0 PA11 ...

Page 47

PIO Controller B Multiplexing Table 11-3. Multiplexing on PIO Controller B (PIOB) I/O Line Peripheral A PB0 PWMH0 PB1 PWMH1 PB2 PWMH2 PWMH3 PB3 TCLK1 PB4 PB5 TIOA1 TIOB1 PB6 RTS0 PB7 PB8 CTS0 PB9 D0 D1 PB10 PB11 ...

Page 48

PIO Controller C Multiplexing Table 11-4. Multiplexing on PIO Controller C (PIOC) I/O Line Peripheral A PC0 A2 PC1 A3 PC2 A4 A5 PC3 A6 PC4 PC5 A7 A8 PC6 A9 PC7 PC8 A10 PC9 A11 A12 PC10 PC11 ...

Page 49

Embedded Peripherals Overview 12.1 Serial Peripheral Interface (SPI) • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and 3-wire EEPROMs – ...

Page 50

Universal Synchronous Asynchronous Receiver Transmitter (USART) • Programmable Baud Rate Generator • 9-bit full-duplex synchronous or asynchronous serial communications – stop bits in Asynchronous Mode stop bits in Synchronous ...

Page 51

Pulse Generation – Delay Timing – Pulse Width Modulation – Up/Down Capabilities – Quadrature Decoder Logic • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • ...

Page 52

High Speed Multimedia Card Interface (HSMCI) • Compatibility with MultiMedia Card Specification Version 4.3 • Compatibility with SD Memory Card Specification Version 2.0 • Compatibility with SDIO Specification Version V2.0. • Compatibility with CE-ATA Specification 1.1 • Cards clock ...

Page 53

Selectable single ended or differential input voltage • Programmable gain for maximum full scale input range • External voltage reference for better accuracy on low voltage inputs • Individual enable and disable of each channel • Multiple trigger sources ...

Page 54

Package Drawings Figure 13-1. 100-ball LQFP Package Drawing SAM3U Series 54 6430CS–ATARM–09-Apr-10 ...

Page 55

Figure 13-2. 100-ball LFBGA Package Drawing 6430CS–ATARM–09-Apr-10 SAM3U Series 55 ...

Page 56

Figure 13-3. 144-lead LQFP Package Drawing Notes: 1. This drawing is for general information only; refer to JEDEe Drawing MS-026 for additional information. 2. The top package body size may be smaller than the bottom package size by as much ...

Page 57

Figure 13-4. 144-ball LFBGA Package Drawing All dimensions are in mm. 6430CS–ATARM–09-Apr-10 SAM3U Series 57 ...

Page 58

Ordering Information Table 14-1. ATSAM3U4/2/1 Ordering Information Ordering Code MRL ATSAM3U4EA-AU A ATSAM3U4EA-CU A ATSAM3U4CA-AU A ATSAM3U4CA-CU A ATSAM3U2EA-AU A ATSAM3U2EA-CU A ATSAM3U2CA-AU A ATSAM3U2CA-CU A ATSAM3U1EA-AU A ATSAM3U1EA-CU A ATSAM3U1CA-AU A ATSAM3U1CA-CU A SAM3U Series 58 Flash (Kbytes) ...

Page 59

Revision History In the tables that follow, the most recent version of the document appears first. “rfo” indicates changes requested during the review and approval loop. Doc. Rev 6430CS Comments Section 2. ”SAM3U Block Section 5. ”Power Considerations”, fixed grammar ...

Page 60

Doc Rev 6430BS Comments Introduction: Section 1. ”SAM3U Description”, Updated: 52 Kbytes of SRAM. 4x USARTs (SAM3U1C/2C/4C have 3 TWIs (SAM3U1C/2C/4C have 1 SPIs SAM3U1C/2C/4C have 4), Table 1-1, “Configuration SAM3U4/3/2C rows FWUP replaces ...

Page 61

Doc. Rev Comments 6430AS First issue 6430CS–ATARM–09-Apr-10 SAM3U Series Change Request Ref. 61 ...

Page 62

Headquarters International Atmel Corporation Atmel Asia 2325 Orchard Parkway Unit 1-5 & 16, 19/F San Jose, CA 95131 BEA Tower, Millennium City 5 USA 418 Kwun Tong Road Tel: 1(408) 441-0311 Kwun Tong, Kowloon Fax: 1(408) 487-2600 Hong Kong Tel: ...

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