m65817afp Mitsumi Electronics, Corp., m65817afp Datasheet

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m65817afp

Manufacturer Part Number
m65817afp
Description
Digital Amplifier Processor Of S-master Technology
Manufacturer
Mitsumi Electronics, Corp.
Datasheet
SYSTEM BLOCK DIAGRAM)
DESCRIPTION
The M65817AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital input signal
to high precise switching-pulse digital output without analog signal.The M65817AFP has built-in 24bit sampling rate converter and
digital-gain-controller.
The M65817AFP enables to realize high precise ( X`tal oscillation precision) full digital amplifier systems combining with power
driver IC.
FEATURES
• Built-in 24bit Sampling Rate Converter.
• Built-in L/R Independent Digital Gain Control.
• Built-in Soft Mute Function with Exponential Approximate-Curve.
• Correspondence for SACD signal (64Fs 1bit,Fs=44.1KHz).
• Output from Sampling Rate Converter.
• 3.3V and 5.0V Power Supply Operation at Output Clock, Input Data, and Control Signal Port
APPLICATION
RECOMMENDED OPERATING CONDITIONS
Logic Block:3.3V±10%,PWM Buffer Block :5.0V±10%
MAIN SPECIFICATION
• Master Clock
• Input Signal Format:
• Input Signal Sampling Rate from 32kHz to 192kHz.
• 8Fs Input Mode:Correspondence for External Digital Filter,Rate Converter Outputs.
• Gain Control Function:
• Third Order
• Sampling Rate Converter Output :Left MSB First /LRch Independent/32BCK
Input Signal Sampling Rate
4 kinds of Digital Input Format.
DVD Receiver, AV Amplifier
* "S-Master" is the digital amplifier technology developed by Sony Corporation. "S-Master" is a trademark of Sony Corporation.
CD
DVD Audio
etc.
SACD
Primary Clock: 256Fs/512Fs
MSB First Right Justified(16/20/24bit),MSB First Left Justified(24bit)
LSB First Right Justified(24bit),I
+30dB to - dB(0.1dB Step until -96dB, -136dB Minimum)
from 32KHz to 192KHz(24bit Maximum).
(16Fs:6bit/5bit)
External
Input
256fsi
/512fsi
LRCK
BCK
DATA
DSD
192kHz
24bit
32kHz
to
Clock
Interface
Converter
Sampling
DSD
Secondary Clock: 1024Fs/512Fs
2
S(24bit)
Rate
MCU I/F
M65817AFP
Control
Level
+30dB
Digital Amplifier Processor of S-Master* Technology
-
to
MITSUBISHI
ELECTRIC
1024fs/512fs
Clock
MITSUBISHI SOUND PROCESSOR ICs
PWM
M65817AFP
Stream
Stream
Power
Driver
Power
Driver
Filter
Filter
LC
LC
1

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m65817afp Summary of contents

Page 1

... DESCRIPTION The M65817AFP is a S-Master technique processor for digital amplifier enable to convert from multi liner-PCM digital input signal to high precise switching-pulse digital output without analog signal.The M65817AFP has built-in 24bit sampling rate converter and digital-gain-controller. The M65817AFP enables to realize high precise ( X`tal oscillation precision) full digital amplifier systems combining with power driver IC ...

Page 2

... (3.3V system) (5V system) MITSUBISHI ELECTRIC M65817AFP 24 OUTL1+ 23 VddL1+ 22 VddL1- (5V system) 21 OUTL1- 20 VssL1- 19 VssL2- 18 OUTL2- 17 VddL2- 16 VddL2+ 15 OUTL2+ 14 VssL2+ 13 VddL 12 VddR 11 VssR1+ 10 OUTR1+ 9 VddR1+ 8 VddR1- 7 OUTR1- 6 VssR1- 5 VssR2- 4 OUTR2- 3 VddR2- (5V system) 2 VddR2+ ...

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... Serial Control MITSUBISHI ELECTRIC M65817AFP Noise PWM Shaper ...

Page 4

... Vdd-0.5 BFVdd=3.0~3.6V IOH3=-3.0mA Vdd-0.5 BFVdd=4.5~5.5V IOH5=-2.0mA Vdd-0.5 BFVdd=3.0~3.6V IOH3=-2.0mA Vdd-0.5 BFVdd=4.5~5.5V IOH5=2.0mA BFVdd=3.0~3.6V IOH3=1.5mA BFVdd=4.5~5.5V IOH5=4.0mA BFVdd=3.0~3.6V IOH3=3.0mA BFVdd=4.5~5.5V IOH5=2.0mA BFVdd=3.0~3.6V IOH3=2.0mA BFVdd=5V MITSUBISHI ELECTRIC M65817AFP Typ. Max Unit Vdd+0.3V ...

Page 5

... Reference Characteristic S/N 103dB(typ) THD+N 0.0015%(typ) MITSUBISHI SOUND PROCESSOR ICs Digital Amplifier Processor of S-Master* Technology - - + + + - - - + + + - Conditions •Input:1kHz sine wave •Fs:Primary, Secondary 48kHz •AC dithering E •DC dithering:0.1% •Gain Data Setting:(Index)10000b/(Mantissa)10000000b •THD+N:Filter 20kHz LPF S/N:Filter 22kHz LPF+JIS-A MITSUBISHI ELECTRIC M65817AFP + - + - 5 ...

Page 6

... I PWM Duty 50% Mute (L :Active) 40 PGMUTE I PWM G-MUTE(L :Active) MITSUBISHI SOUND PROCESSOR ICs Digital Amplifier Processor of S-Master* Technology Input Type - - - - - - - - - - - - - - - - - - - - - - - - - - - Normal - - - H:512Fso Normal - Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt Schmitt MITSUBISHI ELECTRIC M65817AFP Output Current Signal Level 5V/3. ...

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... Input Type Schmitt Schmitt Normal Schmitt Schmitt Schmitt Schmitt Schmitt Normal Normal Normal Normal Normal Normal Normal Normal Normal - Normal Normal Normal Schmitt Schmitt Normal - - - - - Normal - - - Schmitt - - - - - - MITSUBISHI ELECTRIC M65817AFP Output Current Signal Level 5V/3.3V - 5V/3.3V - 5V/3.3V - 5V/3.3V - 5V/3.3V - 5V/3.3V - 5V/3.3V 2mA/1.5mA 5V/3.3V 2mA/1.5mA 5V/3.3V - 5V/3.3V - 5V/3.3V - 5V/3.3V - 5V/3.3V - 5V/3.3V - 5V/3.3V - 5V/3.3V - 5V/3.3V - 5V/3. 5V/3.3V 2mA/1.5mA 5V/3.3V 2mA/1.5mA 5V/3 ...

Page 8

... This clock means output side clock system of rate converter. This clock makes to operate after Rate Converter Block( Gain Control Block, 1-2. SCDT,SCSHIFT,SCLATCH SCDT,SCSHIFT, and SCLATCH are input pins for setting M65817AFP's operation. Input format of SCDT, SCSHIFT and SCLATCH is shown below. Input format of SCDT, SCSHIFT and SCLATCH . ...

Page 9

... MSB LSB 20 cycle LSB MSB 24 cycle 1/fs, 1/2fs, 1/4fs Left LSB MSB 24 cycle 1/fs, 1/2fs, 1/4fs Left 1 BCK LSB MSB 24 cycle MITSUBISHI ELECTRIC M65817AFP Right LSB 24cycle Right LSB MSB 16 cycle MSB LSB 20 cycle LSB MSB 24 cycle Right LSB MSB 24 cycle Right LSB ...

Page 10

... FsoCKO is clock output pin of 1Fs frequency. The output is divided-clock of XfsoIN, and frequency is free-running at power on. FsoCKO pin's clock is utilized for a synchronization in case that have used plural M65817AFP,take a synchronization between M65817AFP and other external devices. Detail explanation is shown in next paragraph, "SYNC ". MITSUBISHI SOUND PROCESSOR ICs ...

Page 11

... Therefore the M65817AFP is operated by the synchronized clocks,Fsol(1fs), Fsil(1fs),and LRCK(1/2/4fs).The M65817AFP detects rise edge of these synchronized-clocks in normal operation, and the M65817AFP does a treatment of resynchronization in case that the cycle has changed. In addition, the M65817AFP re-synchronizes for a synchronized clock, in case that the M65817AFP detects SYNC pin's rise edge ,too ...

Page 12

... Resynchronization treatment, which is same at SYNC function. 1-15. TEST1,TEST2,TEST3 TEST1,TEST2, and TEST3 pins are test input for factory shipping test of M65817AFP. TEST1,TEST2, and TEST3 pins must be tied to "L" level on usual operation. 1-16. Power Supply and GND Power supply and GND routes have 5 isolated lines ...

Page 13

... OUTL1+,OUTL1-,OUTL2+,OUTL2-,OUTR1+,OUTR1-,OUTR2+,OUTR2- OUTL1+,OUTL1-,OUTL2+,OUTL2-,OUTR1+,OUTR1-,OUTR2+ and OUTR2- pins are pulse output converted output signal to PWM data. These pins are connected to external Power Driver ICs. MITSUBISHI SOUND PROCESSOR ICs Digital Amplifier Processor of S-Master* Technology MITSUBISHI ELECTRIC M65817AFP 13 ...

Page 14

... Under `External Rate Converter 8fs` mode, the primary clock side asynchronous detection operates as `forced-disable`. The secondary clock side is operated with synchronization by FsoCKO pin. Then, M65817AFP needs that rising edge of FsoCKO connected from M65817AFP to external sampling rate converter and rising edge of EXWCK connected from external rate converter to M65817AFP are in synchronized phase. ...

Page 15

... MITSUBISHI SOUND PROCESSOR ICs Digital Amplifier Processor of S-Master* Technology SACD operating timing mode L mode1 H mode2 L mode3 H mode4 Input Output D0 XD0 D1 XD1 D2 64fs XD1 D2 D0 XD0 D1 D0 XD0 D1 XD1 64fs XD0:Negative phase data (reversal) MITSUBISHI ELECTRIC M65817AFP XD2 D3 XD3 XD2 D3 XD3 XD2 D3 XD3 ...

Page 16

... FsoCKO pin and be entered each FsoI pins of slave- M65817AFP(inclusive master) with synchronization. Additionally, the master-M65817AFP outputs clock wave from DSD64fs and DSD128fs pins (in this condition, DSDCKIO pin's input level of master-M65817AFP must be "H"), and these clock are entered DSD64fs and DSD128fs pins of slave-M65817AFP(in this condition, DSDCKIO pin's input level of slave-M65817AFP must be “ ...

Page 17

... GAIN12 Gain Data Mantissa (LSB) •Output Limit (bit5,bit6:NSLMT1 , NSLMT2) The M65817AFP has Over Flow Limit function. Over Flow Limit detects of input signal level and limits gain level. Limit value is set by Gain Control Mode :bit5,bit6 ” NSLMT1,NSLMT2” and System2 Mode:bit17"NSOBIT". •The limit value setting of Gain control block and PWM output. ...

Page 18

... Gain value = 20log Digital Amplifier Processor of S-Master* Technology -16 ) Mantissa part:10000000b Mantissa part:00000000b Absolute Output 15.937 | 0.49804687 | -16 0.5*2 | -16 0.00390625*2 infinity zero Mantissa data(decimal value) X MITSUBISHI ELECTRIC M65817AFP Output Level +30.069dB | +6.021dB | 0dB –0.0340dB | –96.330dB | –138.474dB – 128 18 ...

Page 19

... Further, GAIN3 is operated faster than GAIN2 of transition completion("B" or "C" situation in figure), GAIN2 is ignored and data approaches at GAIN3 . Gain 1.0 A (GAIN1 -1.0 MITSUBISHI SOUND PROCESSOR ICs Digital Amplifier Processor of S-Master* Technology t T 10000/10000000b setting (GAIN3) C (GAIN2) Soft Attenuate MITSUBISHI ELECTRIC M65817AFP t 19 ...

Page 20

... MSB First Right Justified Justified 20bit 24bit Don't use 2Fs 4Fs Don`t use 44.1K 48.0K OFF MITSUBISHI ELECTRIC M65817AFP L INIT "L" fixed - - Non-active L Non-active disable ...

Page 21

... Under condition of ASYNCEN1="L", primary side asynchronous detection is ineffective whether the clock is not inputted to FsiI pin, thereby M65817AFP does not operate function under asynchronization, for instance mute operation. However, Primary Side Asynchronous Detection is effective only condition of `SACD-Fsi ` mode. ...

Page 22

... Refer to 6-3-2 Negative-phase Refer to 6-3-3 ROM3 ROM4 Block DC dithering DC dithering Block AC dithering A AC dithering MITSUBISHI ELECTRIC M65817AFP L INIT - "L" fixed - 256Fs enable L disable L non-active L Positive-phase L Non-active L - Non-active L Non-active L Non-active L "L" fixed ...

Page 23

... Under condition of ASYNCEN2="L", secondary side asynchronous detection is ineffective whether FsiI Clock is not inputted, there by M65817AFP does not operate function under asynchronous position, for instance mute operation. •PWM Output Pins L/R Reverse.(bit9: CHSEL). "L": L/R no reverse, "H": L/R reverse. ...

Page 24

... Output load capacity 10 [pF] tpd(EXWCK) Output load capacity 10 [pF] tw(DSDCK) tw(DSDCK) tsu(DATA) mode and 4 th(DATA) mode and 4 tw(SYNC) MITSUBISHI ELECTRIC M65817AFP Min. Typ. Max. Unit 160 nsec 80 ...

Page 25

... EXBCK, EXDATAL, EXDATAR, EXWCK output timing tw(EXBCK) EXBCK EXDATAL EXDATAR EXWCK MITSUBISHI SOUND PROCESSOR ICs Digital Amplifier Processor of S-Master* Technology twl duty (XfsoIN,XfiIN) = tsu(SCDT) th(SCLATCH) tw(BCK) th(DATA) tsu(DATA) tsu(LRCK) th(LRCK) tw(EXBCK) tsu(EXDATA) th(EXDATA) th(EXWCK) tw(EXBCK) tpd(EXDATA) tpd(EXWCK) MITSUBISHI ELECTRIC M65817AFP twh twhl tw(SCLATCH) tsu(SCLATCH) tsu(EXWCK) 25 ...

Page 26

... DSDL DSDR mode3 tw(DSDCK) DSD128fs DSDL DSDR mode4 DSD64fs DSDL DSDR (7) SYNC input timing SYNC MITSUBISHI SOUND PROCESSOR ICs Digital Amplifier Processor of S-Master* Technology tw(DSDCK) th(DATA) tsu(DATA) tw(DSDCK) tsu(DATA) tw(DSDCK) th(DATA) tsu(DATA) tw(DSDCK) th(DATA) tw(SYNC) MITSUBISHI ELECTRIC M65817AFP tw(DSDCK) tsu(DATA) 26 ...

Page 27

... MITSUBISHI SOUND PROCESSOR ICs Digital Amplifier Processor of S-Master* Technology Weight(g) Lead Material 1.58 Alloy Detail F MITSUBISHI ELECTRIC M65817AFP Plastic 80pin 14 20mm body QFP Recommended Mount Pad Dimension in Millimeters Symbol Min Nom Max A – – 3. 0.1 0 – ...

Page 28

... Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. lPlease contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. MITSUBISHI SOUND PROCESSOR ICs Digital Amplifier Processor of S-Master* Technology MITSUBISHI ELECTRIC M65817AFP 28 ...

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