m5m4v4s40ctp-12 Mitsumi Electronics, Corp., m5m4v4s40ctp-12 Datasheet - Page 15

• Manufacturer Part Number: m5m4v4s40ctp-12
• Description: 2-bank 131072-word 16-bit Synchronous Dram
• Manufacturer: Mitsumi Electronics, Corp.

READ
the /CAS Latency from the READ, followed by (BL -1) consecutive output data (Burst Length = BL). The
start address is specified by A7-0, and the address sequence of the burst data is defined by the Burst Type. A
READ command may be applied to any active bank. This allows the row precharge time (tRP) to be hidden
behind continuous output data (in case of BL=4) by interleaving the dual banks. When A8 is high at a READ
command, the auto-precharge (READA) is performed. During READA the READ, WRITE, PRE, and ACT
commands to the same bank are inhibited until the internal precharge is complete. Internal precharge start
timing depends on /CAS Latency. The next ACT command can be issued after tRP from the precharge (PRE).
SDRAM (Rev. 0.3)
OPERATIONAL DESCRIPTION
BANK ACTIVATE
address (BA). A row inside the bank is selected by the row address A8-0. The minimum activation interval
between one bank and the opposite bank is tRRD.
PRECHARGE
command (PREA, PRE + A8=H) can be used to deactivate them at the same time. After tRP from the
precharge, an ACT command can be issued.
Feb ‘97 Preliminary
A READ command can be issued after tRCD from bank activation (ACT). Output data is available after
Note: READA is not allowed for FP burst length operations. The SDRAM must be manually precharged.
The SDRAM has two independent banks. Each bank is activated by the ACT command with the bank
The PRE command deactivates the bank indicated by BA. When both banks are active, the precharge all
Command
CLK
A0-7
A8
BA
DQ
4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM
ACT
Xa
Xa
0
Bank Activation and Precharge All (BL=4, CL=3)
tRRD
tRCD
ACT
Xb
Xb
1
MITSUBISHI ELECTRIC
READ
Y
0
0
M5M4V4S40CTP-12, -15
tRAS
Qa0
Qa1
Precharge all
PRE
Qa2
1
Qa3
tRP
MITSUBISHI LSIs
ACT
Xb
Xb
1
15