gm82c765b ETC-unknow, gm82c765b Datasheet
gm82c765b
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gm82c765b Summary of contents
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... The two XTAL oscillator circuits may be used for the 44-pin PLCC package, while TTL clock inputs must be provided when using the 40-pin DIP package. In the PLCC version of the GM82C765B pins 17 and 40, which were not utilized in DIP version of the GM82C765B, became Change Enable) and (Disk Change) respectively ...
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... I Address line selecting data (=1) or status (=0) ST information (A0 = Logic 0 during I Used by the DMA Controller to transfer data from ST the GM82C765B onto the bus. Logical equivalent to E and A0=1. In special mode, this CS signal is qualified by DMAEN from the Operation Register. 2 GM82C765B 33 ...
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... XT2 XTAL2 21 CLK2 CLOCK2 (condinued on next page) I/O FUNCTION This signal indicates to GM82C765B that data transfer is complete. If DMA operational mode is selected for command execution, TC will be qualified by not in the programmed I/O execution Special mode, qualification by DACK I mode, qualification by DACK ST resister signal DMAEN to be logically true. Note also that mode, TC will be qualified by DMA or non-DMA host operation ...
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... This HCD output, when active low, is MOTOR ON enable for disk drive # mode. This signal O comes from the OPERATIONS Register in the BASE or HCD Special mode, this output the four decoded Unit Selects as specified in the device command syntax. 4 GM82C765B . Each failing edge of active low, is active low, is ...
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... TRACK I This ST input senses status from the disk drive, ST indicating active low when the head is positioned over the beginning of a track marked by an index hole. Input power supply. 5 GM82C765B when bit density is 00 ...
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... NOTE:*:Includes open DRAIN High current drives at VOL=0.4V ...…………………… ( (158 F) - +125 C (257 F) . –0 Vcc +0.3V … 158 ) GM82C765B MIN MAX UNITS 4.5 5.5 V 0.8 V 2.0 V 0.8 V 2 ...
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... PARAMETER Low RD High RD Low RD High RD , Set Up Time to Low LDOR WR , Hold Time from High LDOR WR High High WR High RD High WR Low DACK Low STEP Low STEP 7 GM82C765B MIN MAX UNITS ...
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... WCY specifies WCLK period, dependent on selected data rate 2.4 AC Timing Diagrams (1) READ Timing , CS , DACK . DATA IRQ PARAMETER t Low SRST Data Valid 8 GM82C765B MIN MAX UNITS 2 MCY 96 MCY MCY 32 MCY 40 MCY 500 uS 1000 uS 0 192 MCY 0 ...
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... WRITE Timing CS , DACK ,A0 tAW WR DATA IRQ (3) TERMINAL COUNT (TC) COUNTING DMA or IRQ TC (4) DMA TIMING DMA tMA DACK tMR tMW DATA tWW tDW Data Valid tCR tCW tTC tMCY tAM tAA tMRW tRD tDW Data Valid 9 GM82C765B tWA tWD tWI tDF tWD ...
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... RESET Timing RESET CS (6) DISK DRIVE SELECT TIMING DIRC tDST STEP DSX IDX RDD WD (7) CLOCK Timing CLOCK tR tRST tCA tSTD tSTP tSC tSTU tIDX tRDD tWDD tCY tPH tPH tF 10 GM82C765B ...
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... CLK1 CRYSTAL DIGITAL DATA CLK2 OSc 2 SEPARATOR Fig 1. GM82C765B Internal Block Diagram HOST INTERFACE The host interface is the host microprocessor peripheral bus. This bus is composed of eight control signals and eight data signals. In the special modes, IRQ and DMA request are tri-stated and qualified enable, internally provided by the operations register ...
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... Execution phase. Note also that DB6 and DB7 in the MSR can be polled in-stead of waiting 12uS. When they have the right bit settings, the GM82C765B is ready for com-mands. This might save some time. During the Execution phase, the main status register need not be read ...
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... Register to determine the cause of the interrupt signs is could be a data interrupt or a command terminaton interrupt, either normal or abnormal. If the GM82C765B is in the DMA mode, no inter-rupt signals are generated during the Execution phase. This signifies the beginning of the Result phase. When the first byte of data is read during the Result phase, the Interrupt is auto-matically cleared (IRQ=0) ...
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... FDC, any may be accessed at any time. Only the Master Status Register may be read and used to facilitate the transfer of data between the processor and GM82C765B. The DIO and RQM bits in the Master Status Register indicate when data is ready and in which direction data will be transferred on the data bus ...
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... FDC cannot read the ID field without an error, then this flag is set. During execution of the READ A TRACK command, if the starting sector cannot be found, then this flag is set. During execution of WRITE DATA, WRITE DELETED DATA or RORMAT A TRACK commands. If the FDC detects a WP signal from the FDC, then this flag is set. 15 GM82C765B ...
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... FDD This bit is used to indicate the status of the Side Select signal to the FDD This bit is used to indicate the status of the Unit Select 1 signal to the FDD This bit is used to indicate the status of the Unit Select 0 signal to the FDD 16 GM82C765B PROTECTED ...
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... TABLE 8. OPERATIONS REGISTER OR0 DSEL : Drive Select, if low and MOEN1 = 1, then MOEN2 = 1, then OR1 ( GM82C765B this mist be logic 0 for No defined function in GM82C765B. OR2 SRST : Soft reset, active low. OR3 DMAEN : DMA enable, active in Special and PC AT modes, Qualifies DMA and IRQ outputs and DACK input ...
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... The Control Register may be used in any mode without altering functionality. * BASE MODE After a hardware reset, RST active, the GM82C765B will be held on soft reset, active, with the normally driven signals, DMA request and IRQ request outputs tristated. Base mode may be initiated at this time by a chip access by the host ...
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... SRST RST, but will not affect the value set for the internal timers-HUT, FTL, and SRT. After any reset the GM82C765B, (a hard RST or soft SRST a Polling routine. In between commands (and between step pulse in the SEEK Command), ...
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... It contains the necessary logic to achieve classical 2nd order, type 2, phase locked loop performance. DPLL is used as the Data Separator in the GM82C765B system. Figure 5 illustrates the DPLL implified block diagram. The bit jitter tolerance for the data separator is 60%, Which guarantees an error rate of < ...
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... CLOCK GENERATION This logical block provides all the clocks needed by the GM82C765B. They are: Sampling clock (SCLK), Write clock (WCLK), and the MASTER CLOCK (MCLK). SCLK drives the DPLL Data Separator used during data recovery. This Clocks’s frequency is always 32 times the selected data rate. WCLK is used by the encoder logic to place MFM the serial WD-stream to the disk ...
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... COMMAND PARAMETERS The GM82C765B is capable of performing 15 different commands. Each command is initiated by a multibyte transfer from the processor. The results after execution of the command may also be a multibyte transfer back to the processor. The commands consist of three phases : Command phase, Execution phase, and the Result phase. ...
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... EOT GPL DTL STO ST1 ST2 GM82C765B REMARKS Command Codes Sector ID information prior to command execution. The four bytes are compared against header on floppy disk. Data transfer between FDD and main system Status information after command execution. Sector ID information after command execution ...
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... EOT GPL DTL STO ST1 ST2 GM82C765B REMARKS Command Codes Sector ID information prior to command execution. The four bytes are compared against header on floppy disk. Data transfer between FDD and main system Status information after command execution. Sector ID information after command execution ...
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... US1 US0 N SC GPL D STO ST1 ST2 GM82C765B REMARKS Command Codes The first correct ID information on the cylinder is stored in Data Register. Status information after command execution. Sector ID information after command execution. REMARKS Command Codes Bytes / Sector Sector/Track Gap 3 Filler Byte Floppy Disk Controller (FDC) formats an entire track ...
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... Command Codes US1 US0 C Sector ID information prior to ommand H execution EOT GPL STP Data transfer between FDD and main system STO Status information after command ST1 execution. ST2 C Sector ID information after command H execution GM82C765B REMARKS REMARKS ...
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... HUT N D HLT 27 GM82C765B REMARKS Command Codes Sector ID information prior to command execution. Data transfer between FDD and main system Status information after command execution. Sector ID information after command execution. REMARKS Command Codes Head retracted to Track zero ...
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... low, FM mode is selected high, MFM mode is selected high, a MULTITRACK operation is performed after finishing Read / Write operation on side 0, FDC will automatically start searching for sector 1 on side 1 28 GM82C765B REMARKS Command Codes Status information about the FDC REMARKS ...
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... Note, this function pertains to only one cylinder (the same track) on each side of the diskette. When N=0, then DTL defines the data length which the FDC must treat as a sector. If DTL is smaller than the actual data length in a sector, the 29 GM82C765B ...
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... Less then EOT 0 Equal to EOT 1 1 Less then EOT 1 Equal to EOT Notes : NC (No Change) : The same value the one at the beginning of command execution. LSB (Least Significant Bit): The Least significant bit complemented. 30 GM82C765B ID information at Resul t Phase R ...
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... EOT. If the FDC does not find an ID Address mark on the diskette after it senses index hole for the second time, it sets the MA (Missing Address mark) flag in Status Register (high) and terminates the command. (Status Register 0 has bits 7 and 6 set to 0 and 1 respectively.) 31 GM82C765B ...
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... MFM Mode 1024 2048 4096 128 FM Mode 258 512 256 4 MFM Mode 512 1024 phase. This 32 GM82C765B N SC GPL’ GPL” ...
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... Status Register necessary to have the data available in less then 27 us (FM mode (MFM mode Overrun occurs, the FDC ends the command with bits 7 and 6 of Status Register 0 set to 0 and 1, respectively. SEEK 33 GM82C765B Comments ocessor FDD D ...
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... Status Register 0 is set (high) and the command is terminated. If the Track 0 signal is still low after 77 step pulses have been issued for the GM82C765B,the FDC sets the SE (Seek End) and EC (Equipment Check) flag of Status Register 0 to both 1s (highs), and terminates the command after bits 7 and 6 of Status Register 0 are set to 0 and 1 respectively ...
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... Seek and Recalibrate commands which have no Result phase. When the disk drive has reached the desired head position, the GM82C765B will set the Interrupt line true. The host CPU must then issue a Sense interrupt Status command to determine the actual ...
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... No interrupt is generated during this condition. Bits 6 and 7 (DIO and RQM) in the Main Status Register are both high (1), indicating to the processor that the GM82C765B is in the Result phase and the contents of Status Register 0 (STO) must be read. When the processor reads Status Register 0, it will find an 80 hex, indicating an Invalid command was received ...