SI8220 SILABS [Silicon Laboratories], SI8220 Datasheet
SI8220
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SI8220 Summary of contents
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... CSA component notice 5A approval IEC 60950, 61010, 60601 approved Description The Si8220/ high-performance, functional upgrade for opto- coupled drivers, such as the HCPL-3120 and the HPCL-0302 providing 2 peak output current. It utilizes Silicon Laboratories' proprietary silicon isolation technology, which provides a choice of 2.5, 3.75, or 5.0 kV withstand voltages per UL1577 ...
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... Si8220/21 Functional Block Diagram NC LED Emulator ANODE CATHODE NC 2 ISOLATOR Transmitter Receiver Lockout Si8220/21 Rev. 0.22 VDD VO VO VSS ...
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... Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 6.4. Input Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.5. Parametric Differences between Si8220/21 and HCPL-0302 and HCPL-3120 Opto Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.6. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.7. RF, Magnetic, and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . 18 7. Pin Descriptions (Narrow-Body SOIC Pin Descriptions (Wide-Body SOIC ...
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... Si8220/21 1. Electrical Specifications Table 1. Electrical Characteristics GND –40 to +125 °C; typical specs at 25 ° Parameter DC Specifications Power supply voltage Input current (ON) Input current rising edge hysteresis Input voltage (OFF) Input forward voltage Output resistance high (source) Output resistance low (sink) ...
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... UVLO voltage = VDD HYS 12 200 pF PLH 200 pF PHL L UVLO OFF (0.5 A 200 (2.5 A 200 pF L Time from t START DD_UV+ O CMTI Input ON or OFF Rev. 0.22 Si8220/21 Min Typ Max Units 5.20 5.80 6.30 V 7.50 8.60 9.40 V 9.60 11.1 12.2 V 12.4 13.8 14.8 4.90 5.52 6.0 V 7.20 8.10 8.70 V 9.40 10.1 10.9 V 11.6 12.8 13.8 — 280 — ...
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... Si8220/21 2. Test Circuits INPUT Measure GND 200 ns INPUT WAVEFORM Figure 1. IOL Sink Current Test Circuit INPUT Measure GND 200 ns INPUT WAVEFORM Figure 2. IOH Source Current Test Circuit 6 VDD = 15 V VDD IN_ OUT_ Si822x SCHOTTKY VSS 1 µF 10 µF ...
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... RMS Symbol Test Condition L(IO1) 1 L(IO2) DIN IEC CTI 60112/VDE 0303 Part MHz Rev. 0.22 Si8220/21 for 1 sec. RMS for 1 sec. RMS for 1 sec. RMS Value Unit WB NB SOIC-16 SOIC-8 8.0 min 4.9 min mm 8.0 min 4.01 min mm ...
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... Si8220/21 Table 4. IEC 60664-1 (VDE 0844 Part 2) Ratings Parameter Basic isolation group Material Group Rated Mains Voltages < 150 V Rated Mains Voltages < 300 V Installation Classification Rated Mains Voltages < 400 V Rated Mains Voltages < 600 V Table 5. IEC 60747-5-2 Insulation Characteristics for Si82xxxC* Symbol Parameter ...
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... C = 200 pF, input a 2 MHz 50% duty cycle square wave Symbol Min WB SOIC-16 — 100 JA VDDI = 5.5 V VDDA, VDDB = 100 Case Temperature (ºC) Rev. 0.22 Si8220/21 Max Min Typ Unit WB NB SOIC-16 SOIC-8 — — 150 150 — — — ...
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... Si8220/ Figure 4. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Table 8. Absolute Maximum Ratings Parameter 2 Storage temperature Operating temperature Output supply voltage Output voltage Output current drive Input current Lead solder temperature (10 s) ...
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... The Si8220/ functional upgrade for popular opto-isolated drivers, such as the Avago HPCL-3120, HPCL- 0302, Toshiba TLP350, and others. The operation of an Si8220/21 channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up ...
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... Si8220/21 5. Technical Description 5.1. Device Behavior Truth tables for the Si8220/21 are summarized in Table 9. Table 9. Si8220/21 Truth Table Summary Cathode Anode Diode Current ( Hi Hi-Z GND GND VF VF GND1 VF GND1 VF Note: “X” = don’t care. 5.2. Device Startup Output V is held low during power-up until V ...
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... Under Voltage Lockout (UVLO) The UVLO circuit unconditionally drives V through 11, upon power up, the Si8220/21 is maintained in UVLO until VDD rises above VDD down, the Si8220/21 enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDD – VDD ). HYS V DDUV+ 3 ...
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... Layout Considerations It is most important to minimize ringing in the drive path and noise on the V minimize parasitic inductance in these paths by locating the Si8220/21 as close to the device it is driving as possible. In addition, the V supply and ground trace paths must be kept short. For this reason, the use of power DD and ground planes is highly recommended ...
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... Vdd Control Input – 3 – 10 – Equation 3. 500 1,000 1,500 Frequency (KHz) OPTO DRIVER N ANODE 2 CATHODE 3 Open Drain or Collector N/C 4 Figure 13. Opto Driver Input Circuit Rev. 0.22 Si8220/21 2,000 2,500 15 ...
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... Figure 15, which are more efficient than those of Figures 13 and 14. As shown, S1 represents any suitable switch, such as a BJT or MOSFET, analog transmission gate, processor I/O, etc. Also, note that the Si8220/21 input can be driven from the I/O port of any MCU or FPGA capable of sourcing a minimum (see Figure 15C). ...
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... However, high CMR opto driver designs that overdrive the LED (see Figure 14) may require increasing the value limit input current max. In addition, there is no benefit in driving the Si8220/21 input diode into reverse bias when in the off state. Consequently, opto driver circuits using this technique should either leave the negative bias circuitry unpopulated or modify the circuitry (e ...
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... In theory, data transmission errors can occur if the magnetic field is too large and the field is too close to the isolator. However, in actual use, the Si8220/21 devices provide extremely high immunity to external magnetic fields and have been independently evaluated to withstand magnetic fields of at least 1000 A/m according to the IEC 61000-4-8 and IEC 61000-4-9 specifications ...
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... ANODE CATHODE Top View Figure 17. Pin Configuration Description follows the signal applied to this input with respect to the O follows the signal applied to ANODE with respect to this input. O (24 V max). SS Rev. 0.22 Si8220/21 . This terminal is typically DD 19 ...
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... External MOSFET source connection and ground reference for V SS typically connected to ground but may be tied to a negative or positive voltage Output signal Output-side power supply input referenced *Note: No Connect. These pins are not internally connected. 20 Si8220 1 16 CATHODE ...
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... Input Configuration (2 = Opto-input) Peak Output Current (0=2.5A, 1=0.5A) UVLO* level (A=5V, B=8V, C=10V, D=12.5V) Insulation Rating (A=1kV,B=2.5kV,C=3.75kV,D=5kV) Product Revision Temp Range (I=-40 to +125C) Package Type (S=SOIC) Package Extension (1=Narrow Body) *UVLO= Under Voltage Lock Out Figure 18. Si8220/21 OPN Naming Convention Si82CIUV-R-TPn Rev. 0.22 Si8220/21 21 ...
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... Opto input Si8221DC-A-IS Opto input *Note: All packages are RoHS-compliant. Moisture sensitivity level is MSL3 with peak reflow temperature of 260 °C according to the JEDEC industry standard classifications and peak solder temperature. 22 Table 15. Si8220/21 Ordering Guide* Ordering Options Peak Output UVLO Insulation Current ...
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... Figure 19 illustrates the package details for the Si822x. Table 16 lists the values for the dimensions shown in the illustration. Figure 19. 8-pin Small Outline Integrated Circuit (SOIC) Package Table 16. Package Diagram Dimensions Millimeters Symbol Min Max A 1.35 1.75 A1 0.10 0.25 A2 1.40 REF 1.55 REF B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BSC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 Rev. 0.22 Si8220/21 23 ...
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... Si8220/21 11. Land Pattern: 8-Pin Narrow Body SOIC Figure 20 illustrates the recommended land pattern details for the Si822x in an 8-pin narrow-body SOIC. Table 17 lists the values for the dimensions shown in the illustration. Figure 20. PCB Land Pattern: 8-Pin Narrow Body SOIC Table 17. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC) ...
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... Figure 21 illustrates the package details for the Si822x Digital Isolator. Table 18 lists the values for the dimensions shown in the illustration. Table 18. Package Diagram Dimensions Figure 21. 16-Pin Wide Body SOIC Millimeters Symbol Min Max A — 2.65 A1 0.1 0.3 D 10.3 BSC E 10.3 BSC E1 7.5 BSC b 0.31 0.51 c 0.20 0.33 e 1.27 BSC h 0.25 0.75 L 0.4 1.27 0° 7° Rev. 0.22 Si8220/21 25 ...
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... Si8220/21 13. Land Pattern: 16-Pin Wide-Body SOIC Figure 22 illustrates the recommended land pattern details for the Si822x in a 16-pin wide-body SOIC. Table 19 lists the values for the dimensions shown in the illustration. Table 19. 16-Pin Wide Body SOIC Land Pattern Dimensions Dimension Notes: 1 ...
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... N : OTES Rev. 0.22 Si8220/21 27 ...
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... Si8220/ ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...