SC2542EVB SEMTECH [Semtech Corporation], SC2542EVB Datasheet - Page 13

• Manufacturer Part Number: SC2542EVB
• Description: High Performance Wide Input Range Dual Synchronous Buck Controller
• Manufacturer: SEMTECH [Semtech Corporation]

Under Voltage Lock Out (UVLO)
The UVLO circuitry monitors Vcc and the soft start begins
once Vcc ramps up above 5.5V. There is a built in 400mV
hysteresis voltage for the UVLO ramp down threshold.
The gate driver output will be in “tri-state”(both high side
and low side MOSFET off) once Vcc ramps down bellow
5.1V (typical), and the soft start cap will be discharged by
internal 15uA current sink.
Over Voltage Protection (OVP)
The OVP circuitry monitors the feedback voltages, If ei-
ther feedback voltage exceeds 0.89V, the OVP condition
is registered. Under this condition, the DRVH pins will be
pulled low, and the DRVL pins will be pulled high. This will
create a “crow bar” condition for the input power rail in
case the high side MOSFET is failed short. The crow bar
operation may trip the input supply to prevent the load
from seeing more voltage.
Minimum Pulse Width Setting
In skip mode operation, the top FET driver always sends
out a pulse which is wider than the DCM pulse to keep
the load in regulation. This forces the SC2542 to oper-
ate in skip mode and improves the light load efficiency.
To set minimum pulse, one can use a simple formula:
Setting Tpulse is 80% of normal pulse wide.
For example, with 24V input, 5V output and 200khz op-
erating frequency. The normal pulse is 1.04 uS. To set
Tpulse = 0.83uS, one can use:
Power Good
The power good is an open collector output. The PWRGD
pin is pulled low at start up if any of the two feedback
voltages are below 90% of the regulation level. The ramp
down threshold of the signal is 80% of the regulation
POWER MANAGEMENT
Applications Information (Cont.)
2005 Semtech Corp.
Rmin =
Tpulse
150
Rmin(k ) =
(
pC
Vin
)
=
. 0
Tpulse
150
83
150
S
(
pC
(
pC
X
Vin
)
24
)
V
= 133k
13
target. External pull up is required for the PWRGD pin,
and the pull up resistor should be chosen such that the
pin does not sink more than 1mA when PWRGD is low.
Main Control Loop Design
The goal of compensation is to shape the frequency re-
sponse of the buck converter to achieve a better DC
accuracy and a faster transient response, while main-
taining the loop stability.
The block diagram in Figure 10 represents the control
loop of a buck converter designed with the SC2542. The
control loop consists of a compensator, a PWM modula-
tor, and an LC filter.
The LC filter and the PWM modulator represent the small
signal model of the buck converter operating at fixed
switching frequency. The transfer function of the model
is given by:
Figure 10. Block diagram of the control loop.
where V
internal ramp, and R is the equivalent load.
The model is a second order system with a finite DC gain,
a complex pole pair at Fo, and an ESR zero at Fz, as
shown in Figure 11. The locations of the poles and zero
are determined by:
Z
REF
IN
is the input voltage, V
REF
Z
+
-
EA
V
V
O
C
V
V
ERROUT
MODULATOR
IN
m
PW
1
1
SL
m
is the amplitude of the
SR
/
R
ESR
Resr
S
C
L
2
LC
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SC2542
C
Vo