hm5216165tt-10h ETC-unknow, hm5216165tt-10h Datasheet
hm5216165tt-10h
Available stocks
Related parts for hm5216165tt-10h
hm5216165tt-10h Summary of contents
Page 1
... Interleave (BL = 1/2/4/8) Programmable CAS latency: 1/2/3 Byte control by DQMU and DQML Refresh cycles: 4096 refresh cycles/ variations of refresh Auto refresh Self refresh Ordering Information Type No. HM5216165TT-10H HM5216165TT-12 100 MHz/83 MHz Frequency Package 100 MHz 400-mil 50-pin plastic TSOP II (TTP-50D) 83 MHz 16-bit 2-bank) ADE-203-280C (Z) Rev ...
Page 2
... HM5216165 Series Pin Arrangement V CC I/O0 I/ I/O2 I/ I/O4 I/ I/O6 I/ DQML WE CAS RAS CS A11 A10 HM5216165TT Series I/O15 3 48 I/O14 I/O13 6 45 I/O12 I/O11 9 42 I/O10 I/O9 12 ...
Page 3
Pin Description Pin name A0 to A11 I/O0 to I/O15 CS RAS CAS WE DQMU DQML CLK CKE HM5216165 Series Function Address input Row address A0 to A10 Column ...
Page 4
HM5216165 Series Block Diagram Column address counter Row decoder Memory array Bank 0 2048 row X 256 column X 16 bit Input Output buffer buffer I/O0 – I/O15 4 A0 – A11 A0 – A7 Column address buffer 2048 row ...
Page 5
Pin Functions CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is ...
Page 6
HM5216165 Series Command Operation Command Truth Table The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins. Function Ignore command No operation Burst stop in full page Column address and read command Read ...
Page 7
Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY7) and the bank select address (A11) become the burst write start address. When the ...
Page 8
HM5216165 Series CKE Truth Table Current state Function Active Clock suspend mode entry Any Clock suspend Clock suspend Clock suspend mode exit Idle Auto refresh command Idle Self refresh entry Idle Power down entry Self-refresh Self refresh exit Power down ...
Page 9
Low. Since self refresh is performed internally and automatically, external refresh operations are unnecessary. Power down mode entry: When this command is executed during the IDLE state, the synchronous DRAM enters power down mode. In power down mode, power consumption ...
Page 10
HM5216165 Series CS RAS CAS WE Current state Row active Read ...
Page 11
CS RAS CAS WE Current state Write Write with H auto-precharge ...
Page 12
HM5216165 Series From [PRECHARGE] To [DESL], [NOR] or [BST]: When these commands are executed, the synchronous DRAM enters the IDLE state after t has elapsed from the completion of precharge. RP From [IDLE] To [DESL], [NOP], [BST], [PRE] or [PALL]: ...
Page 13
From [READ with AUTO PRECHARGE] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the synchronous DRAM then enters precharge mode. To [ACTV]: This command makes other banks bank active. (However, an interval of ...
Page 14
HM5216165 Series Simplified State Diagram MODE REGISTER SET (on full page) Write CKE_ WRITE SUSPEND CKE WRITE WITH AP CKE_ WRITEA SUSPEND CKE POWER POWER APPLIED ON Automatic transition after completion of command. Transition resulting from command input. Note: 1. ...
Page 15
Mode Register Configuration The mode register is set by the input to the address pins (A0 to A11) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A11, A10, ...
Page 16
HM5216165 Series Burst Sequence Burst length = 2 Starting Ad. Addressing(decimal) A0 Sequence Burst length = 8 Starting Ad. Addressing(decimal Sequence ...
Page 17
Operation of HM5216165 Series Read/Write Operations Bank active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. Either bank 0 or bank 1 is activated according ...
Page 18
HM5216165 Series Burst Length CLK t RCD Command READ ACTV Address Row Column out out 0 out out 0 out 1 out 2 out 3 Dout out 0 out ...
Page 19
Single write A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0 single write operation, data is only written to the column address (AY0 to AY7) and the bank select address (A11) specified by ...
Page 20
HM5216165 Series Auto Precharge Read with auto precharge: In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after ...
Page 21
Write with auto precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after ...
Page 22
HM5216165 Series CAS Latency = 1, Burst Length = full page CLK Command I/O (output) out out CAS Latency = 2, Burst Length = full page CLK Command I/O (output) out out CAS Latency = 3, Burst Length = full ...
Page 23
Burst stop command at burst write: The burst stop command (BST command) is used to stop data input during a full-page burst write. No data is written in the same cycle as the BST command and in subsequent cycles. In ...
Page 24
HM5216165 Series Command Intervals Read command to Read command interval: Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can ...
Page 25
Write command to Write command interval: Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval ...
Page 26
HM5216165 Series Read command to Write command interval: Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after ...
Page 27
Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 cycle. ...
Page 28
HM5216165 Series commands is one cycle. However, since the output buffer then becomes High-Z after the cycles defined there is a possibility that burst read data output will be interrupted, if the precharge command is input HZP ...
Page 29
READ to PRECHARGE Command Interval (same bank): To stop output data CAS Latency = 1, Burst Length = CLK READ PRE/PALL Command Dout out A0 CAS Latency = 2, Burst Length = ...
Page 30
HM5216165 Series Write command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cycle. WRITE to PRECHARGE ...
Page 31
Bank active command interval: Same bank: The interval between the two bank-active commands must be no less than t In the case of different bank-active commands: The interval between the two bank-active commands must be no less than t . ...
Page 32
HM5216165 Series Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than t CLK Command MRS Address CODE (A0-A11) Mode Register Set 32 . RSA ACTV ...
Page 33
DQM Control The DQMU and DQML mask the lower and upper bytes of the I/O data, respectively. The timing of DQMU/DQML is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQMU/DQML. ...
Page 34
HM5216165 Series Refresh Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external ...
Page 35
Absolute Maximum Ratings Parameter Voltage on any pin relative Supply voltage relative Short circuit output current Power dissipation Operating temperature Storage temperature Note: 1. Respect Recommended DC Operating Conditions (Ta = ...
Page 36
HM5216165 Series DC Characteristics ( Parameter Symbol Operating current I CC1 Standby current I CC2 (Bank Disable) Active standby current I CC3 (Bank active) Burst operating current (CAS latency = 1) I CC4 (CAS ...
Page 37
Capacitance ( Parameter Input capacitance (Address) Input capacitance (Signals) Output capacitance (I/O) Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQMU/DQML = V to disable Dout ...
Page 38
HM5216165 Series AC Characteristics ( Parameter Command (CS, RAS, CAS, WE, DQM) setup time Command (CS, RAS, CAS, WE, DQM) hold time Ref/Active to Ref/Active command period Active to precharge command period Active to ...
Page 39
Relationship Between Frequency and Minimum Latency Parameter Frequency (MHz) t (ns) CK Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) ...
Page 40
HM5216165 Series Relationship Between Frequency and Minimum Latency (cont) Parameter Frequency (MHz) t (ns) CK Register set to active command CS to command disable Power down exit to command input Burst stop to output valid data hold (CAS latency = ...
Page 41
Timing Waveforms Read Cycle CKH CKL CLK V IH CKE t RCD RAS CAS ...
Page 42
HM5216165 Series Write Cycle CKH CKL CLK V IH CKE t RCD RAS CAS ...
Page 43
Mode Register Set Cycle CLK V CKE IH CS RAS CAS WE A11(BS) Address valid code DQMU /DQML I/O(output) I/O(input RSA Precharge Mode Bank 1 If needed register Active Set ...
Page 44
HM5216165 Series Read Cycle/Write Cycle CLK CKE RAS CAS WE A11(BS) Address R:a C:a R:b DQMU /DQML I/O a (output) I/O (input) Bank 0 Bank 0 Bank 1 Active Read Active ...
Page 45
Read/Single Write Cycle CLK V CKE IH CS RAS CAS WE A11(BS) R:a C:a Address DQMU /DQML I/O (input) I/O (output) Bank 0 Bank 0 Active Read CKE RAS CAS WE A11(BS) ...
Page 46
HM5216165 Series Read/Burst Write Cycle CLK V CKE IH CS RAS CAS WE A11(BS) R:a C:a Address DQMU /DQML I/O (input) I/O (output) Bank 0 Bank 0 Active Read CKE RAS CAS ...
Page 47
Full Page Read/Write Cycle CLK V CKE IH CS RAS CAS WE A11(BS) Address R:a C:a R:b DQMU /DQML I/O a (output) I/O (input) Bank 0 Bank 0 Bank 1 Active Read Active ...
Page 48
HM5216165 Series Auto Refresh Cycle CLK CKE RAS CAS WE A11(BS) Address A10=1 DQMU /DQML I/O(input) I/O(output Auto Refresh Precharge If needed Self Refresh Cycle CLK CKE CKE Low CS ...
Page 49
Clock Suspend Mode t CESP CLK CKE CS RAS CAS WE A11(BS) Address R:a DQMU /DQML I/O (output) I/O (input) Bank0 Active clock Active clock Active suspend start suspend end CKE CS RAS CAS ...
Page 50
HM5216165 Series Power Down Mode CLK CKE CS RAS CAS WE A11(BS) Address A10=1 DQMU /DQML I/O(input) I/O(output Precharge command If needed Power Up Sequence CLK V CKE IH CS RAS CAS WE Address ...
Page 51
... Package Dimensions HM5216165TT Series (TTP-50D) 20.95 21.35 Max 50 1 0.80 0.27 0.07 0.13 M 0.25 0.05 1.15 Max 0.10 Dimension including the plating thickness Base material dimension 26 25 11.76 0.20 0 – 5 Hitachi Code JEDEC EIAJ Weight (reference value) HM5216165 Series Unit: mm 0.80 0.50 0.10 TTP-50D — — 0. ...
Page 52
HM5216165 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, ...
Page 53
Revision Record Rev. Date Contents of Modification 0.0 Jul. 29, 1994 Initial issue 0.1 Oct. 20, 1995 Change of Command Truth Table Change of Function Truth Table Change of Simplified State Diagram Change of figures for Operation of HM5216165 Series ...
Page 54
HM5216165 Series Revision Record (cont) Rev. Date Contents of Modification 2.0 Jun. 20, 1997 Deletion of HM5216165-10/15 Series 3.0 Nov. 1997 Change of Subtitle 54 Drawn by Approved by T. Takemura S. Ishikawa ...