mx25l1605azmi-15g Macronix International Co., mx25l1605azmi-15g Datasheet
mx25l1605azmi-15g
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mx25l1605azmi-15g Summary of contents
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The MX25L1605A product will be phase-out, and is not recommended for new design. The MX25L1605A will be migrated to MX25L1605D, which is a functional compatible product. Please refer to MX25L1605D datasheet for new design. P/N: PM1211 MX25L1605A MX25L1605A DATASHEET 1 ...
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The MX25L1605A product will be phase-out, and is not recommended for new design. The MX25L1605A will be migrated to MX25L1605D, which is a functional compatible product. Please refer to MX25L1605D datasheet for new design. FEATURES GENERAL • Serial Peripheral Interface ...
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Status Register Feature • Electronic Identification - JEDEC 2-byte Device ID - RES command, 1-byte Device ID HARDWARE FEATURES • SCLK Input - Serial clock input • SI Input - Serial Data Input • SO Output - Serial Data ...
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PIN CONFIGURATIONS 16-PIN SOP (300mil) 1 SCLK HOLD# 16 VCC CS# 7 GND 8-LAND SON (8x6mm) ...
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BLOCK DIAGRAM Generator SI CS# SCLK P/N: PM1211 Address Memory Array Page Buffer Data Register Y-Decoder SRAM Buffer Mode State HV Logic Machine Generator Clock Generator 5 MX25L1605A Output Sense Amplifier Buffer SO REV. 1.6, APR. 18, 2008 ...
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DATA PROTECTION The MX25L1605A is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. ...
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Table 1. Protected Area Sizes Status bit BP2 BP1 BP0 P/N: PM1211 Protection Area MX25L1605A 0 ...
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HOLD FEATURE HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select(CS#) keeping ...
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Table 2. COMMAND DEFINITION COMMAND WREN WRDI (byte) (write (write Enable) disable) 1st 06 Hex 04 Hex 2nd 3rd 4th 5th Action sets the reset the output the (WEL) (WEL) write write enable enable latch bit latch bit COMMAND SE ...
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Table 3. Memory Organization Bolck Sector Address Range 511 1FF000h 1FFFFFh 31 496 1F0000h 1F0FFFh 495 1EF000h 1EFFFFh 30 480 1E0000h 1E0FFFh 479 1DF000h 1DFFFFh 29 464 1D0000h 1D0FFFh 463 1CF000h 1CFFFFh 28 448 1C0000h 1C0FFFh 447 1BF000h 1BFFFFh 27 ...
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DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby ...
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COMMAND DESCRIPTION (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set ...
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Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously recommended to check the Write in ...
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Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ...
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Note: If SRWD bit=1 but WP# is low impossible to write the Status Register even if the WEL bit has previously been set rejected to write the Status Register and not be executed. Hardware Protected Mode ...
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The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 ...
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The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 ...
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Read Electronic Manufacturer ID & Device ID (REMS) The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS instruction is very ...
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POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down ...
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature - for Commercial grade Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential Figure 3.Maximum Negative Overshoot Waveform 20ns Vss Vss - 2.0V 20ns ...
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Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing referance level 0.8VCC 0.2VCC Figure 6. OUTPUT LOADING DEVICE UNDER TEST P/N: PM1211 MX25L1605A Output timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time ...
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Table 5. DC CHARACTERISTICS (Temperature = - for Industrial grade, Temperature = SYMBOL PARAMETER NOTES ILI Input Load Current ILO Output Leakage Current ISB1 VCC Standby Current ISB2 Deep Power-down Current ICC1 VCC Read ICC2 VCC ...
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Table 6. AC CHARACTERISTICS (Temperature = - for Industrial grade, Temperature = Symbol Alt. Parameter fSCLK fC Clock Frequency for the following instructions: FAST_READ, PP, SE, BE, CE, DP, RES,RDP WREN, WRDI, RDID, RDSR, WRSR fRSCLK ...
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Table 7. Power-Up Timing and VWI Threshold Symbol Parameter tVSL(1) VCC(min) to CS# low tPUW(1) Time delay to Write instruction VWI(1) Write Inhibit Voltage Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the ...
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Figure 7. Serial Input Timing CS# tCHSL SCLK tDVCH SI High-Z SO Figure 8. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1211 MX25L1605A tSLCH tCHSH tCHDX tCLCH MSB LSB tCH tCLQV tCL tQLQH tQHQL 25 ...
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Figure 9. Hold Timing CS# SCLK SO HOLD "don't care" during HOLD operation. Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tWHSL CS SCLK SI High-Z SO P/N: PM1211 tHLCH ...
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Figure 11. Write Enable (WREN) Sequence (Command 06) CS# SCLK SI SO Figure 12. Write Disable (WRDI) Sequence (Command 04) CS# SCLK SI SO Figure 13. Read Identification (RDID) Sequence (Command 9F) CS SCLK Command SI High-Z ...
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Figure 14. Read Status Register (RDSR) Sequence (Command 05) CS SCLK command SI High-Z SO Figure 15. Write Status Register (WRSR) Sequence (Command 01) CS# SCLK SI SO Figure 16. Read Data Bytes (READ) Sequence (Command 03) ...
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Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B) CS SCLK Command SI 0B High SCLK Dummy Byte P/N: PM1211 ...
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Figure 18. Page Program (PP) Sequence (Command 02) CS SCLK Command SI CS SCLK Data Byte MSB P/N: PM1211 3 ...
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Figure 19. Sector Erase (SE) Sequence (Command 20) CS# SCLK SI Note: SE command is 20(hex). Figure 20. Block Erase (BE) Sequence (Command 52 or D8) CS# SCLK SI Note: BE command D8(hex). P/N: PM1211 MX25L1605A 0 ...
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Figure 21. Chip Erase (CE) Sequence (Command 60 or C7) CS# SCLK SI Note: CE command is 60(hex) or C7(hex). Figure 22. Deep Power-down (DP) Sequence (Command B9) CS SCLK SI Figure 23. Release from Deep Power-down and ...
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Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB) CS SCLK SI High-Z SO Figure 25. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90) CS SCLK Command SI 90 High-Z SO ...
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Figure 26. Power-up Timing (max) Program, Erase and Write Commands are Ignored Chip Selection is Not Allowed V CC (min) Reset State of the Flash V WI P/N: PM1211 MX25L1605A Read Command is Device is fully ...
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RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) ...
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ERASE AND PROGRAMMING PERFORMANCE PARAMETER Write Status Register Cycle Time Sector erase Time Block erase Time Chip Erase Time Page Program Time Erase/Program Cycle Note: 1. Typical program and erase time assumes the following conditions 3.3V, and checker ...
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... PART NO. CLOCK (MHz) MX25L1605AMC-12 85 MX25L1605AMC-12G 85 MX25L1605AMI-12 85 MX25L1605AMI-12G 85 MX25L1605AZMC-12G 85 MX25L1605AZMI-12G 85 MX25L1605AM2C-12 85 MX25L1605AM2C-12G 85 MX25L1605AM2I-12 85 MX25L1605AM2I-12G 85 MX25L1605AMC-15 70 MX25L1605AMC-15G 70 MX25L1605AMI-15 70 MX25L1605AMI-15G 70 MX25L1605AZMC-15G 70 MX25L1605AZMI-15G 70 MX25L1605AM2C-15 70 MX25L1605AM2C-15G 70 MX25L1605AM2I-15 70 MX25L1605AM2I-15G 70 P/N: PM1211 MX25L1605A OPERATING STANDBY Temperature PACKAGE CURRENT MAX. CURRENT MAX. (mA) (uA ...
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PART NAME DESCRIPTION 1605A P/N: PM1211 MX25L1605A OPTION: G: Pb-free blank: normal SPEED: 12: 85MHz 15: 70MHz TEMPERATURE RANGE: C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: ZM: SON M: ...
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PACKAGE INFORMATION P/N: PM1211 MX25L1605A 39 REV. 1.6, APR. 18, 2008 ...
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P/N: PM1211 MX25L1605A 40 REV. 1.6, APR. 18, 2008 ...
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P/N: PM1211 MX25L1605A 41 REV. 1.6, APR. 18, 2008 ...
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REVISION HISTORY Revision No. Description 1.0 1. Removed "Advanced Information" title 2. Added description about Pb-free device is RoHS compliant 1.1 1. Added 85MHz spec 2. Standby current is reduced from 50uA(max) to 20uA(max) 3. Modified tSE:90ms(typ)/270ms(max)-->60ms(typ)/120ms(max) ; tBE:3s(max)-->2s(max); tCE:32s(typ)/64s(max)-->14s(typ)/30s(max) ...
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... Macronix's products in the prohibited applications ACRONIX NTERNATIONAL Headquarters Macronix America, Inc. Macronix Japan Cayman Islands Ltd. Macronix (Hong Kong) Co., Limited. http : //www.macronix.com MX25L1605A C L O., TD. Taipei Office Macronix Europe N.V. Singapore Office MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 43 ...