mx25l1635dzni-10g Macronix International Co., mx25l1635dzni-10g Datasheet
mx25l1635dzni-10g
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P/N: PM1374 MX25L1635D DATASHEET 1 MX25L1635D REV. 1.7, MAR. 30, 2009 ...
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FEATURES .................................................................................................................................................................. 5 GENERAL ................................................................................................................................................................. 5 PERFORMANCE ...................................................................................................................................................... 5 SOFTWARE FEATURES .......................................................................................................................................... 5 HARDWARE FEATURES ......................................................................................................................................... 6 GENERAL DESCRIPTION ......................................................................................................................................... 7 Table 1. Additional Feature Comparison ................................................................................................................... 7 PIN CONFIGURATIONS ............................................................................................................................................. 8 PIN DESCRIPTION ...................................................................................................................................................... 8 BLOCK DIAGRAM ....................................................................................................................................................... 9 ...
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Table 7. ID Definitions ............................................................................................................................................ 24 (19) Enter Secured OTP (ENSO) ........................................................................................................................... 24 (20) Exit Secured OTP (EXSO) .............................................................................................................................. 24 (21) Read Security Register (RDSCUR) ................................................................................................................. 25 Table 8. Security Register Definition ....................................................................................................................... 25 (22) Write Security Register (WRSCUR) ................................................................................................................ ...
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Figure 29. Power-up Timing .................................................................................................................................... 41 Table 11. Power-Up Timing ..................................................................................................................................... 41 INITIAL DELIVERY STATE ..................................................................................................................................... 41 RECOMMENDED OPERATING CONDITIONS ......................................................................................................... 42 ERASE AND PROGRAMMING PERFORMANCE .................................................................................................... 43 LATCH-UP CHARACTERISTICS .............................................................................................................................. 43 ORDERING INFORMATION ...................................................................................................................................... 44 PART NAME DESCRIPTION ..................................................................................................................................... ...
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CMOS MXSMIO FEATURES GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 16M:16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O read mode) structure or 4,194,304 x 4 ...
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HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • SO/SIO1 - Serial Data Output or Serial Data ...
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GENERAL DESCRIPTION The MX25L1635D are 16,777,216 bit serial Flash memory, which is configured as 2,097,152 x 8 internally. When two or four I/O read mode, the structure becomes 8,388,608 bits 4,194,304 bits x 4. ...
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PIN CONFIGURATIONS 16-PIN SOP (300mil) 1 SCLK NC/SIO3 16 VCC 2 SI/SIO0 CS# 7 GND 10 8 WP#/SIO2 SO/SIO1 9 8-LAND WSON (6x5mm) ...
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BLOCK DIAGRAM SI/SIO0 CS# WP#/SIO2 NC/SIO3 SCLK SO/SIO1 P/N: PM1374 Address Generator Memory Array Page Buffer Data Register Y-Decoder SRAM Buffer Mode State HV Logic Machine Generator Clock Generator 9 MX25L1635D Sense Amplifier Output Buffer REV. 1.7, MAR. 30, 2009 ...
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DATA PROTECTION The MX25L1635D is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. ...
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Table 2. Protected Area Sizes Status bit BP3 BP2 BP1 BP0 ...
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Memory Organization Table 4. Memory Organization Block Sector Address Range 511 1FF000h 496 1F0000h 495 1EF000h 480 1E0000h 479 1DF000h 464 1D0000h 463 1CF000h 448 1C0000h 447 1BF000h ...
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DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended op- eration. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the ...
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COMMAND DESCRIPTION Table 5. Command Set Command WREN (write WRDI (write (byte) enable) disable) 1st byte 06 (hex) 04 (hex) 2nd byte 3rd byte 4th byte 5th byte sets the resets the (WEL) write (WEL) write enable latch enable latch ...
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RDSCUR WRSCUR Command (read security (write security (byte) register) register) 1st byte 2B (hex) 2F (hex) 2nd byte 3rd byte 4th byte to read value to set the lock- of security down bit as register "1" (once lock- down, cannot ...
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Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP, CP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set ...
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Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously recommended to check the Write in ...
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Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ...
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Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by ...
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I/O Read Mode (4READ) The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to "1" before seding the 4READ instruction.The address is latched ...
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Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the ...
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Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit ...
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Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter- ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode ...
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After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in figure 31. ...
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Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of ...
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POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down ...
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This ...
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Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing referance level 0.8VCC 0.2VCC Figure 5. OUTPUT LOADING DEVICE UNDER TEST CL=30pF Including jig capacitance (CL=15pF Including jig capacitance for 86/104MHz, 84MHz@2xI/O and 80MHz@4xI/O) P/N: PM1374 Output timing referance level ...
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Table 9. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) SYMBOL PARAMETER ILI Input Load Current ILO Output Leakage Current ISB1 VCC Standby Current Deep Power-down ISB2 Current ICC1 VCC Read VCC Program ...
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Table 10. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) Symbol Alt. Parameter Clock Frequency for the following instructions: fSCLK fC FAST_READ, PP, SE, BE, CE, DP, RES,RDP WREN, WRDI, RDID, RDSR, WRSR ...
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Timing Analysis Figure 6. Serial Input Timing CS# tCHSL SCLK tDVCH SI SO Figure 7. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1374 tSLCH tCHSH tCHDX tCLCH MSB High-Z tCH tCLQV 31 MX25L1635D tSHSL tSHCH ...
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Figure 8. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 WP# tWHSL CS SCLK SI High-Z SO Figure 9. Write Enable (WREN) Sequence (Command 06) CS# SCLK SI SO Figure 10. Write Disable (WRDI) Sequence (Command ...
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Figure 11. Read Identification (RDID) Sequence (Command 9F) CS SCLK Command SI High-Z SO Figure 12. Read Status Register (RDSR) Sequence (Command 05) CS SCLK command SI 05 High-Z SO Figure 13. Write ...
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Figure 14. Read Data Bytes (READ) Sequence (Command 03) CS SCLK command 03 SI High-Z SO Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B) CS SCLK Command SI 0B High-Z ...
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Figure 16 I/O Read Mode Sequence (Command BB) CS SCLK 8 Bit Instruction BB(hex) SI/SIO0 High Impedance SO/SIO1 Figure 17 I/O Read Mode Sequence (Command EB) CS ...
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Figure 18 I/O Read enhance performance Mode Sequence (Command EB) CS SCLK 8 Bit Instruction EB(hex) SI/SIO0 High Impedance SO/SIO1 High Impedance WP#/SIO2 High Impedance NC/SIO3 CS# n+1 ........... SCLK 6 Address cycles ...
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Figure 19. Page Program (PP) Sequence (Command 02) CS SCLK Command SI CS SCLK Data Byte MSB Figure 20. 4 ...
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Figure 21. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD) CS SCLK Command SI AD (hex) 24-bit address high impedance S0 Note: (1) During CP mode, the valid commands are CP command ...
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Figure 24. Chip Erase (CE) Sequence (Command 60 or C7) CS# SCLK SI Note: CE command is 60(hex) or C7(hex). Figure 25. Deep Power-down (DP) Sequence (Command B9) CS SCLK SI Figure 26. Release from Deep Power-down and ...
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Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB) CS SCLK Command SI High-Z SO Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command DF) CS ...
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Figure 29. Power-up Timing (max) Chip Selection is Not Allowed V CC (min) Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V. Table 11. Power-Up Timing Symbol Parameter tVSL(1) VCC(min) to CS# low Note: 1. ...
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RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) ...
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ERASE AND PROGRAMMING PERFORMANCE PARAMETER Write Status Register Cycle Time Sector Erase Cycle Time Block Erase Cycle Time Chip Erase Cycle Time Byte Program Time (via page program command) Page Program Cycle Time Erase/Program Cycle Note: 1. Typical program and ...
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... ORDERING INFORMATION CLOCK PART NO. (MHz) MX25L1635DMI-12G 86 MX25L1635DM2I-12G 86 MX25L1635DZNI-10G 104 MX25L1635DM2I-10G 104 P/N: PM1374 OPERATING STANDBY CURRENT CURRENT TEMPERATURE MAX. (mA) MAX. (uA -40°C~85° -40°C~85° -40°C~85° -40°C~85°C 44 MX25L1635D PACKAGE Remark 16-SOP Pb-free 8-SOP Pb-free (200mil) 8-WSON ...
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PART NAME DESCRIPTION P/N: PM1374 1635D OPTION: G: Pb-free SPEED: 12: 86MHz 10: 104MHz TEMPERATURE RANGE: I: Industrial (-40°C to 85°C) PACKAGE: ZN: WSON M: 300mil 16-SOP M2: 200mil 8-SOP DENSITY & MODE: ...
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PACKAGE INFORMATION P/N: PM1374 MX25L1635D 46 REV. 1.7, MAR. 30, 2009 ...
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P/N: PM1374 MX25L1635D 47 REV. 1.7, MAR. 30, 2009 ...
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P/N: PM1374 MX25L1635D 48 REV. 1.7, MAR. 30, 2009 ...
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REVISION HISTORY Revision No. Description 1.0 1. Removed "Advanced Information" on page 1 1.1 1. Corrected wording 2. Added the description of SRWD bit for factory default 1.2 1. Correct typo 1.3 1. Changed tSHSL spec from 30/50ns to 15/50ns ...
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... Macronix's products in the prohibited applications. Copyright© Macronix International Co. Ltd. 2007~2009. All Rights Reserved. Macronix, MXIC, MXIC Logo, MX Logo, MXSMIO, are trademarks or registered trademarks of Macronix International Co., Ltd.. The names and brands of other companies are for identification purposes only and may be claimed as the property of the respective companies ...