mx25l1655d Macronix International Co., mx25l1655d Datasheet
mx25l1655d
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mx25l1655d Summary of contents
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... SECURITY SERIAL FLASH SPECIFICATION P/N: PM1430 MX25L1655D 1 MX25L1655D REV. 1.2, MAR. 11, 2009 ...
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... Deep Power-down (DP) .................................................................................................................................. 21 (19) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ................................................... 22 (20) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4) ................................................. 22 Table 5. ID Definitions ............................................................................................................................................ 23 (21) Enter Secured OTP (ENSO) ........................................................................................................................... 23 (22) Exit Secured OTP (EXSO) .............................................................................................................................. 23 P/N: PM1430 MX25L1655D Contents 2 REV. 1.2, MAR. 11, 2009 ...
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... Figure 28. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB Figure 29. Release from Deep Power-down (RDP) Sequence (Command AB) .................................................... 40 Figure 30. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command DF) .............. 40 Figure 31. Power-up Timing .................................................................................................................................... 41 P/N: PM1430 MX25L1655D 3 REV. 1.2, MAR. 11, 2009 ...
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... Table 11. Power-Up Timing and VWI Threshold ..................................................................................................... 41 INITIAL DELIVERY STATE ..................................................................................................................................... 41 RECOMMENDED OPERATING CONDITIONS ........................................................................................ 42 ERASE AND PROGRAMMING PERFORMANCE ................................................................................... 43 LATCH-UP CHARACTERISTICS ............................................................................................................. 43 ORDERING INFORMATION ..................................................................................................................... 44 PART NAME DESCRIPTION .................................................................................................................... 45 PACKAGE INFORMATION ....................................................................................................................... 46 REVISION HISTORY ................................................................................................................................ 48 P/N: PM1430 MX25L1655D 4 REV. 1.2, MAR. 11, 2009 ...
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... Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) P/N: PM1430 MX25L1655D TM (SERIAL MULTI I/O) FLASH MEMORY 5 REV. 1.2, MAR. 11, 2009 ...
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... NC pin or serial data Input/Output for 4 x I/O read mode • PACKAGE - 8-pin SOP (200mil) - 24-ball BGA * - All Pb-free devices are RoHS Compliant Please contact Macronix sales for specific information regarding this Advanced Security Features *Advanced Information P/N: PM1430 MX25L1655D 6 REV. 1.2, MAR. 11, 2009 ...
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... The MX25L1655D are 16,777,216 bit serial Flash memory, which is configured as 2,097,152 x 8 internally. When two or four I/O read mode, the structure becomes 8,388,608 bits 4,194,304 bits x 4. The MX25L1655D feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO) ...
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... SCLK 6 GND 4 SI/SIO0 5 Please contact Macronix sales for specific information regarding 24-ball TFBGA (6x8 mm) package pin con- figuration. P/N: PM1430 MX25L1655D PIN DESCRIPTION SYMBOL DESCRIPTION CS# Chip Select Serial Data Input (for 1xI/O)/ Serial Data SI/SIO0 Input & Output (for 2xI/O or 4xI/O read ...
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... BLOCK DIAGRAM Address Generator SI/SIO0 CS# WP#/SIO2 NC/SIO3 SCLK SO/SIO1 P/N: PM1430 Memory Array Page Buffer Data Register Y-Decoder SRAM Buffer Mode State HV Logic Machine Generator Clock Generator 9 MX25L1655D Sense Amplifier Output Buffer REV. 1.2, MAR. 11, 2009 ...
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... DATA PROTECTION The MX25L1655D is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory con- tents only occurs after successful completion of specific command sequences ...
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... Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512-bit se- cured OTP mode, array access is not allowed. Table 2. 512-bit Secured OTP Definition Address range Size xxxx00~xxxx0F 128-bit xxxx10~xxxx3F 384-bit P/N: PM1430 MX25L1655D Standard Factory Lock ESN (electrical serial number) N/A 11 Customer Lock Determined by customer REV. 1.2, MAR. 11, 2009 ...
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... P/N: PM1430 MX25L1655D Block Sector 1FFFFFh 239 : 14 1F0FFFh 224 1EFFFFh 223 : 13 1E0FFFh 208 1DFFFFh 207 : 12 1D0FFFh 192 1CFFFFh 191 : 11 1C0FFFh 176 1BFFFFh 175 : 10 1B0FFFh ...
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... CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1430 shift in MSB 13 MX25L1655D shift out MSB REV. 1.2, MAR. 11, 2009 ...
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... B9 (hex) AB (hex) AB (hex enters deep release from to read out power down deep power 1-byte Device mode down mode ID 14 MX25L1655D RDBLOCK UNLOCK (read Block READ (read (chip Write Lock data) unprotect) status) FB (hex) F3 (hex) 03 (hex) AD1 AD1 (A23-A16) AD2 ...
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... RY/ register) BY#) 2B (hex) 2F (hex) 70 (hex) to read value to set the to enable SO of security lock-down bit to output RY/ register as "1" (once BY# during lock-down, CP mode cannot be updated) 15 MX25L1655D DSRY (disable SO to output RY/ BY#) 80 (hex) to disable SO to output RY/ BY# during CP mode REV. 1.2, MAR. 11, 2009 ...
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... The sequence of issuing RDSR instruction is: CS# goes low→sending RDSR instruction code→Status Register data out on SO (see Figure 12) The definition of the status register bits is as below: P/N: PM1430 MX25L1655D 16 REV. 1.2, MAR. 11, 2009 ...
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... The sequence of issuing RDBLOCK instruction is: CS# goes low →send RDBLOCK (FBh) instruction →send 3 ad- dress bytes to assign one block on SI pin→read block's protection lock status bit on SO pin→ CS# goes high. (see Figure 16) P/N: PM1430 MX25L1655D bit4 bit3 bit2 x ...
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... CS# to high at any time during data out (see Figure 18 for 2 x I/O Read Mode Timing Waveform). While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM1430 MX25L1655D 18 REV. 1.2, MAR. 11, 2009 ...
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... A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); P/N: PM1430 MX25L1655D 19 REV. 1.2, MAR. 11, 2009 ...
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... The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) in- struction must execute to set the Write Enable Latch (WEL) bit. The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and SIO3 as address and data input, which can improve programer performance and the effectiveness P/N: PM1430 MX25L1655D 20 REV. 1.2, MAR. 11, 2009 ...
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... Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high. (see Fig- P/N: PM1430 MX25L1655D 21 REV. 1.2, MAR. 11, 2009 ...
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... Device ID values are listed in Table of ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read con- tinuously, alternating from one to the other. The instruction is completed by driving CS# high. P/N: PM1430 MX25L1655D 22 REV. 1.2, MAR. 11, 2009 ...
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... Continuously Program Mode (CP mode) bit. The Continuously Program Mode bit indicates the status of CP mode, "0" indicates not in CP mode; "1" indicates in CP mode. P/N: PM1430 memory type C2 26 electronic ID 26 device MX25L1655D memory density 15 REV. 1.2, MAR. 11, 2009 ...
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... Continuously Program mode x (CP mode) 0=normal Program mode reserved reserved 1=CP mode (default=0) volatile bit volatile bit volatile bit 24 MX25L1655D bit1 bit0 LDSO Secrured OTP x (indicate if indicator bit lock-down 0 = not lock non-factory down lock 1 = lock-down 1 = factory (cannot lock program/erase ...
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... The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the figure of "power-up timing". Note stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend- ed. (generally around 0.1uF) P/N: PM1430 MX25L1655D 25 REV. 1.2, MAR. 11, 2009 ...
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... CIN Input Capacitance COUT Output Capacitance P/N: PM1430 Industrial grade Figure 3. Maximum Positive Overshoot Waveform 20ns Vcc + 2.0V Vcc MIN. TYP MAX MX25L1655D VALUE -40°C to 85°C -55°C to 125°C -0.5V to 4.6V -0.5V to 4.6V -0.5V to 4.6V 20ns 20ns 20ns UNIT CONDITIONS pF VIN = 0V pF VOUT = 0V REV. 1.2, MAR. 11, 2009 ...
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... TEST CL=30pF Including jig capacitance (CL=15pF Including jig capacitance for 104MHz, 75MHz@2xI/O and 75MHz@4xI/O) P/N: PM1430 Output timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time are <5ns 2.7K ohm CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT 27 MX25L1655D 0.5VCC +3.3V REV. 1.2, MAR. 11, 2009 ...
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... V 0.7VCC VCC+0.4 V 0.4 V VCC-0 MX25L1655D VCC = VCC Max, VIN = VCC or GND VCC = VCC Max, VIN = VCC or GND VIN = VCC or GND, CS# = VCC VIN = VCC or GND, CS# = VCC f=104MHz, fQ=75MHz (4 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open f=66MHz, fT=75MHz (2 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open f=33MHz, SCLK=0 ...
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... Block Erase Cycle Time tCE Chip Erase Cycle Time Notes: 1. tCH + tCL must be greater than or equal Value guaranteed by characterization, not 100% tested in production. 3. tSHSL=15ns from read instruction, tSHSL=50ns from Write/Erase/Program instruction. 4. Test condition is shown as Figure 4, 5. P/N: PM1430 MX25L1655D Min. Typ. D.C. D.C. 4.7 4.7 0.1 0.1 ...
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... Timing Analysis Figure 6. Serial Input Timing CS# tCHSL SCLK tDVCH SI High-Z SO Figure 7. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1430 tSLCH tCHSH tCHDX tCLCH MSB LSB tCH tCLQV tQLQH tQHQL 30 MX25L1655D tSHSL tSHCH tCHCL tCL tSHQZ LSB REV. 1.2, MAR. 11, 2009 ...
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... Figure 9. Write Enable (WREN) Sequence (Command 06) CS# SCLK SI SO Figure 10. Write Disable (WRDI) Sequence (Command 04) CS# SCLK SI SO P/N: PM1430 Command 06 High Command 04 High-Z 31 MX25L1655D tSHWL REV. 1.2, MAR. 11, 2009 ...
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... Status Register Out MSB MSB Bit Address Command MSB 32 MX25L1655D Device Identification Status Register Out REV. 1.2, MAR. 11, 2009 ...
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... MSB 7 MSB Address Bytes 1 Dummy Bytes Dummy MSB 33 MX25L1655D Data Out 1 Data Out Block Protection Lock status out ...
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... P/N: PM1430 BIT ADDRESS DATA OUT MSB MSB 34 MX25L1655D DATA OUT MSB REV. 1.2, MAR. 11, 2009 ...
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... P5 P1 bit21, bit17..bit1 address P6 P2 bit22, bit18..bit2 address P7 P3 bit23, bit19..bit3 35 MX25L1655D Data Output data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... n Data Output data bit4, bit0, bit4.... data bit5 bit1, bit5 ...
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... P5 P1 bit5 bit1, bit5.... data P6 P2 bit6 bit2, bit6.... data P7 P3 bit7 bit3, bit7.... P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00 MX25L1655D n Data Output data bit4, bit0, bit4.... data bit5 bit1, bit5.... data bit6 bit2, bit6.... data bit7 bit3, bit7.... REV. 1.2, MAR. 11, 2009 ...
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... Command 6 Address cycle Byte MX25L1655D Data Byte Data Byte 256 Data Data Data Data Byte 2 ...
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... Byte n-1, Byte n Command (1) Byte 0, Byte1 status ( Command 24 Bit Address MSB Command 24 Bit Address MSB 38 MX25L1655D (hex) 05 (hex REV. 1.2, MAR. 11, 2009 ...
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... DP Command B9 Stand-by Mode Dummy Bytes MSB Electronic Signature Out MSB Deep Power-down Mode 39 MX25L1655D Deep Power-down Mode RES2 Stand-by Mode REV. 1.2, MAR. 11, 2009 ...
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... Dummy Bytes Manufacturer MSB MSB 40 MX25L1655D Stand-by Mode 47 Device MSB REV. 1.2, MAR. 11, 2009 ...
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... Note: 1. The parameter is characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1430 MX25L1655D Device is fully accessible tVSL Min. Max. ...
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... For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1430 tSLCH tDVCH tCHDX MSB IN High Impedance Figure A. AC Timing at Device Power-Up Notes Min MX25L1655D tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN Max. Unit 20 500000 us/V REV. 1.2, MAR. 11, 2009 ...
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... LATCH-UP CHARACTERISTICS Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1430 MX25L1655D Min. TYP. (1) Max. (2) 40 100 60 300 ...
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... ORDERING INFORMATION CLOCK PART NO. (MHz) MX25L1655DM2I-12G 86 Please contact Macronix sales for specific information regarding 24-ball TFBGA (6x8 mm) ordering information. P/N: PM1430 OPERATING STANDBY CURRENT CURRENT TEMPERATURE MAX. (mA) MAX. (uA -40°C~85°C 44 MX25L1655D PACKAGE Remark 8-SOP Pb-free (200mil) REV. 1.2, MAR. 11, 2009 ...
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... Please contact Macronix sales for specific information regarding 24-ball TFBGA (6x8mm) part name description P/N: PM1430 1655D OPTION: G: Pb-free SPEED: 12: 86MHz TEMPERATURE RANGE: I: Industrial (-40°C to 85°C) PACKAGE: M2: 200mil 8-SOP DENSITY & MODE: 1655D: 16Mb Security type TYPE DEVICE: 25: Serial Flash 45 MX25L1655D REV. 1.2, MAR. 11, 2009 ...
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... PACKAGE INFORMATION P/N: PM1430 MX25L1655D 46 REV. 1.2, MAR. 11, 2009 ...
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... P/N: PM1430 MX25L1655D 47 REV. 1.2, MAR. 11, 2009 ...
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... Revised tCH/tCL Min. value and Notes 3 in Table 10. 7. Changed VWI parameter description 1.2 1. Removed "Low Vcc write inhibit" function 2. Removed QE bit/SRWD bit status register information 3. Removed ICC3 4. Modified tCH/tCL from 4.5/4.5ns to 4.7/4.7ns 5. Modified data retention from 10 years to 20 years P/N: PM1430 MX25L1655D Page P6,8,44,45 P47 P15,17,33 P6,8,44,45 P17 P29 P41 ...
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... Macronix Europe N.V. Koningin Astridlaan 59, Bus 1 1780 Wemmel Belgium Tel: +32-2-456-8020 Fax: +32-2-456-8021 Macronix Offices : USA Macronix America, Inc. 680 North McCarthy Blvd. Milpitas, CA 95035, U.S.A. Tel: +1-408-262-8887 Fax: +1-408-262-8810 MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 49 MX25L1655D ...