zl10038 ETC-unknow, zl10038 Datasheet
zl10038
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zl10038 Summary of contents
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... ZL10038 simply requires a crystal reference and operates from supply designed as a 'simple to use' stand-alone tuner, requiring no training algorithms or user/demodulator intervention to optimize performance. The ZL10038 can be used with an advanced modulation demodulator to create a highly-integrated front-end solution, operating from 1-45 MS/s. Figure 1 - Block Diagram 1 Zarlink Semiconductor Inc ...
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... ZL10038 Figure 2 - Typical Application Circuit 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Band Switch Algorithm (VSD Bit 3.4.16 LO Main- & Sub-Band Selection (V2:0 & S3:0 Bits 3.4.17 LO Sample Rate (LS2:0 Bits 3.4.18 LO Window Level (WS, WH2:0 & WL2:0 Bits 3.4.19 LO Window Relaxation (WRE Bit 3.4.20 LO Test (TL Bit 4.0 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1 Power-On Software Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ZL10038 Table of Contents Bits Zarlink Semiconductor Inc. ...
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... Determining the Values of BF and 4.3.4 Filter Bandwidth Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.4 Programming Sequence for Filter Bandwidth Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.0 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 Crystal Oscillator Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2 Absolute Maximum Ratings 6.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4 DC Characteristics 6.5 AC Characteristics ZL10038 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 11 - Free Running LO Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12 - Copper Dimensions for Optimum Heat Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 13 - Paste Mask for Reduced Paste Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 14 - Typical Oscillator Arrangement with Optional Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 15 - Typical Arrangement for External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ZL10038 List of Figures 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 14 - Division Ratios Set with Bits Table 15 - Frequency Bands and VCO Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table Sample Rate Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table Window Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table Recommended Window Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 19 - Crystal Capacitor Values for 4 MHz and 10 MHz Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ZL10038 List of Tables 6 Zarlink Semiconductor Inc. Data Sheet ...
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... QDC 3 QOUT 4 QOUT 5 VccBB 6 VccBB 7 IOUT 8 IOUT 9 IDC 10 IDC Name No. ADD 16 CNT 40 DIGDEC 17 DRIVE 20 IDC 9 IDC 10 IOUT 7 IOUT 8 LOCK 25 LOTEST 38 ZL10038 No. Name No. Name 11 SLEEP 21 PUMP 12 SCL 22 N/C 13 SDA 23 Vvar 14 XTAL XTALCAP 25 LOCK 16 ADD 26 VccRF 17 DIGDEC 27 RFBYPASS 18 VccDIG 28 RFBYPASS 19 VccTUNE 29 VccRF ...
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... SLEEP In 12 SCL In 13 SDA Out ZL10038 Function Q Channel DC offset correction capacitor. Configuration and value as per application diagram (see Figure 2). Q Channel baseband differential outputs. AC couple outputs as per applications diagram (see Figure 2 voltage supply for Baseband +5 v voltage supply for Baseband ...
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... Varactor tuning +5 v supply 20 DRIVE IO Loop amplifier output and input pins 21 PUMP IO 22 N/C Not connected. Ground externally. 23 Vvar In LO tuning voltage input ZL10038 Function 9 Zarlink Semiconductor Inc. Data sheet Schematics DIGDEC DIGDEC 400 Ω 400 Ω XTAL XTAL 100 Ω 100 Ω XTALCAP XTALCAP 0 ...
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... RF differential inputs. 31 RFIN In AC couple input. Matching circuitry as per applications 32 RFIN In diagram. 33 N/C Not connected. Ground externally. 34 RFAGC In RF analogue gain control input ZL10038 Function 10 Zarlink Semiconductor Inc. Data sheet Schematics P0/P1 P0/P1 LOCK LOCK CMOS Digital Output CMOS Digital Output VccRF VccRF Vref Vref 5k ...
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... P1 Out ‘0’ = disabled (high impedance) ‘1’ = enabled Bonded to paddle. Production continuity 40 CNT test for paddle soldering Note: Exposed paddle on rear of package must be connected to GND. ZL10038 Function Same configuration as pin 24 Zarlink Semiconductor Inc. Data sheet Schematics PTEST PTEST ...
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... Functional Description 2.1 Quadrature Down-Converter In normal applications the tuner RF input frequency of 950 - 2150 MHz is fed directly to the ZL10038 RF input preamplifier stage, through an appropriate impedance match. The input preamplifier is optimized for NF, S11 and signal handling. The signal handling of the front end is designed such that no tracking filter is required to offer immunity to input composite overload ...
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... AGC Functions The ZL10038 contains an analogue RF AGC combined with digitally controlled gain for RF, baseband pre-filter and post-filter, as described in Figure 4. The baseband AGC is controlled by the I²C bus and is divided into pre- and post-baseband filter stages, each of which have 12 gain adjust in 4.2 dB steps. ...
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... MHz -10 -20 -30 -40 -50 20 (RF gain adjust = +0 dB, prefilter = +4.2 dB and postfilter = 4.2 dB, baseband filter bandwidth = 22 MHz) ZL10038 Gain setting dB Figure 6 - Variation in IIP2 with AGC Setting Gain setting dB ...
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... The output of each channel stage is designed for low impedance drive capability and low intermodulation and can be loaded either differentially or single-ended; in the case of single-ended load the unused output should be unloaded. The maximum output load is defined in the Electrical Characteristics Table. ZL10038 -70 -60 -50 ...
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... RF Bypass The ZL10038 provides an independent bypass function, which can be used for driving a second receiver module. The electrical characteristics of the RF input are unchanged by the state of the RF bypass. The bypass provides a differential buffered output from the input signal with a nominal 3.5 dB gain. The unused output should be terminated as in Figure 2 on page 2 ...
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... Local Oscillator The LO on the ZL10038 is fully integrated and consists of three oscillator stages, each with 16 sub-bands. These are arranged such that the regions of operation for optimum phase noise are continuous over the required tuning range of 950 to 2150 MHz and over the specified operating ambient conditions and process spread. ...
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... There is a further hardware lock flag (LOCK output, pin 25; see “3.1.1” on page 20) which generates a logic ‘0’ if the tuning controller detects the varactor line voltage lies within the ‘tune unlock’ window and set to logic ‘1’. In other states this output is high impedance. ZL10038 100 1000 ...
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... Control Logic The ZL10038 is controlled by an I²C data bus and can function as a slave receiver or slave transmitter compatible with 3V3 levels. Data and Clock are input on the SDA and SCL lines respectively as defined by I²C bus standard. The device can either accept data (slave receiver, write mode), or send data (slave transmitter, read mode). The LSB of the address byte (R/W) sets the device into write mode logic ‘ ...
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... PD register bit, the two functions being logically OR’ed. Feedback on the status of the ZL10038 is provided through eight bits in the status byte register and the phase lock state is also available on the LOCK output pin (as well as the FL register bit). ...
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... Read Register The ZL10038 status can be read by addressing the device in its slave transmitter mode by setting the LSB of the address byte (the R/W bit one. After the master transmits the correct address byte, the ZL10038 will acknowledge its address, and transmit data in response to further clocks on the SCL input. If the master responds ...
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... LSB of the address byte (the R/W bit zero. After the master transmits the correct address byte, the ZL10038 will acknowledge its address, and accept data in response to further clocks on the SCL line. At the end of each byte, the ZL10038 will generate the acknowledge bit. The master can at this point, generate a stop condition, or further clocks on the SCL line if further registers are to be programmed ...
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... Baseband filter FLL reference frequency select TL C1,C0 Charge pump current select CC Charge pump control CLR Control logic reset LEN RF bypass enable LS2-0 Tuning control sampling rate adjust MA1,MA0 Variable address bits P0, P1 External switching ports ZL10038 MA1 MA0 ...
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... The baseband pre-filter gain is programmed by setting BA1:0, bits-4 & register byte-4 as required. See also Figure 4, “AGC Control Structure” on page 13. 3.4.6 Baseband Post-Filter Gain (BG1:0 Bits) The baseband post-filter gain is programmed by setting BG1:0, bits-2 & register byte-4 as required. See also Figure 4, “AGC Control Structure” on page 13. ZL10038 Bits) 14 ...
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... Bit-7 of byte-13 controls the PD register bit which is an alternative to the SLEEP pin (see “SLEEP - Pin 11” on page 20). Setting the PD bit to a logic ‘1’ shuts down the analogue sections of the ZL10038 effecting a saving of about 2/3rds of the power required for normal operation. A logic ’0’ restores normal operation. With either hardware or software power-down, all register settings are unaffected ...
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... Register bits R4:0 control the reference divider ratios as shown in Table 14. They are programmed through bit-4 to bit-0 respectively, in byte- Table 14 - Division Ratios Set with Bits ZL10038 VCO sub-bands ±210 (reset state) ±365 ±625 Invalid Setting ±210 ±365 ±625 ±1065 Table 13 - Charge Pump Currents ...
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... VSD bit, if required, allowing manual control. The VSD bit is programmed using byte-9, bit-7. The default is for the controller to be enabled, VSD = ‘0’, and to disable the controller a logic ‘1’ is written to this bit. ZL10038 (sect. 2.4) on page 16 and “Symbol Rate and Filter 27 Zarlink Semiconductor Inc ...
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... Table 15 - Frequency Bands and VCO Gain ZL10038 VCO1 VCO2 Min Max Kvco Min Max Kvco 690 699 881 892 6.9 8.9 697 708 892 905 7.3 9.3 ...
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... The WH2:0 bits set the upper levels and the WL2:0 bits set the lower levels in each case. Please see “Power-On Software Initialization” (sect. 4.1) on page 30 for recommended values. WH2 WL2 Key: ZL10038 LS2 LS1 LS0 Sample Rate comp ...
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... Channel frequency/PLL comparison frequency. 4.3 Symbol Rate and Filter Calculations 4.3.1 Determining the Filter Bandwidth from the Symbol Rate f = (α * symbol rate)/(2 where: α = 1.35 for DVB or 1.20 for DSS, and is the roll-off of the raised-root cosine filter in the transmitter, ZL10038 WH1 WH0 WL2 WL1 WL0 ...
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... These equations can give non-integer results so rounding must be performed. The values for BR should be rounded DOWN to the nearest integer this ensures that programmable bandwidth will not be below the desired bandwidth due to rounding. ZL10038 ≤ 35 MHz × --- - ...
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... Byte 7: Set BF6:1 to the value derived in 4.3.3.2, “Calculating the Value of BF“ on page 32. c. Byte 6: Set RSD = 1 to disable baseband filter resistor switching. This must happen no sooner than a certain time after (b.). This minimum time equals BR/( byte BR and f is the reference crystal frequency. xtal ZL10038 – = ...
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... Figure 12 - Copper Dimensions for Optimum Heat Transfer Figure 13 - Paste Mask for Reduced Paste Coverage The ZL10038 uses the 40-pin QFN package with a thermal ‘paddle’ in the base, which has a very high thermal conductivity to the die, as well as low electrical resistance to the Vee connections. The ZL10038 has a fairly high power density, and if the excess heat is not efficiently removed, it will rapidly overheat beyond the 125° ...
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... Gnd if an oscillator output is required. Output is from the crystal/capacitor junction. Table 19 - Crystal Capacitor Values for 4 MHz and 10 MHz Operation (component numbering refers to the example schematic, Figure 2) Figure 14 - Typical Oscillator Arrangement with Optional Output Figure 15 - Typical Arrangement for External Oscillator ZL10038 4 MHz Zarlink Semiconductor Inc ...
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... Voltage on LOTEST Voltage on IOUT, QOUT, IDC, QDC and inverted equivalents Voltage on P1 Voltage at DIGDEC Voltage on PUMP Voltage on SLEEP and P0 Voltage on ADD, XTAL, XTALCAP and LOCK Sink current ESD protection, pins 31 & 32 pins 1-30, 33-40 ZL10038 Symbol Min. -0.3 5.5 -55 150 STG 125 j -0.3 6 -0.3 VccTUNE+0.3 -0 ...
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... IDC Input high voltage Input low voltage Input current SCL, SDA: 12, 13 Leakage current Hysteresis Output voltage SDA: 13 Charge pump leakage PUMP: 21 Charge pump current ZL10038 Symbol Min. Typ. Max. Units Normal operating conditions 210 259 mA 228 281 mA 243 300 mA ...
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... Input low voltage Input DC current RFAGC: 34 Leakage current Output impedance LOTEST: 38 Bias voltage 6.5 AC Characteristics Characteristic Noise figure, DSB Variation in NF with RF gain adjust Conversion gain Maximum Minimum AGC control range ZL10038 Min. Typ. Max. VccTUNE-0.2 0.3 10 200 - 0.5 DigDec-0 -0 ...
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... LO reference sideband spur level on I & Q outputs In band LO leakage to RF input Gain NF OPIP3 OPIP2 Output return loss Forward isolation Reverse isolation In band LO leakage Converter Input return loss (pins RFIN & RFIN) ZL10038 Min. Typ. Max. Units -35 dBc See -40 dBc See -15 dBc ...
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... See Figure 8, RF gain adjust = +4 dB, prefilter = +4.2 dB and postfilter = 0 dB, RFG = 1, BA1 = 0, BA0 = 1, BG1 = 0, BG0 = 0 3. ’Baseband defined IM2’. AGC set to deliver an output of 0.5 Vp-p with an input CW @ frequency fc of -25 dBm. Two undesired tones at fc+146 and fc+155 MHz @ -11 dBm generating output intermodulation spur at 9 MHz. Baseband filter at 22 MHz bandwidth setting. ZL10038 Min. Typ. Max. ...
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... PLL loop bandwidth ~15 kHz, comparison frequency MHz. 15. Integrated rms LO jitter measured from 1 kHz to 15 MHz, PLL loop bandwidth 15 kHz. Varactor voltage = 3.5 volts. 16. RSD = 0 for 8 MHz <= fset <= 20 MHz, RSD = 1 for 20 MHz <= fset <= 35 MHz. ZL10038 40 Zarlink Semiconductor Inc. Data sheet ...
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Zarlink Semiconductor 2004 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors ...