SI52144 SILABS [Silicon Laboratories], SI52144 Datasheet

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SI52144

Manufacturer Part Number
SI52144
Description
PCI-EXPRESS GEN 1, GEN 2, & GEN 3 CLOCK QUAD OUTPUT GENERATOR
Manufacturer
SILABS [Silicon Laboratories]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI52144-A01
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
SI52144-A01AGM
0
Part Number:
SI52144-A01AGMR
0
PCI-E
O
Features
Applications
Description
The Si52144 is a spread-controlled PCIe clock generator that can source
four PCIe clocks simultaneously. The device has four hardware output
enable control inputs for enabling the respective differential outputs on the
fly while powered on along with the spread control hardware pin to enable
spread for EMI reduction. In addition to the hardware control pins, I
programmability is also available to promptly achieve optimum clock
signal integrity through skew and edge rate control on true, compliment,
or both differential outputs as well as amplitude control.
Functional Block Diagram
Preliminary Rev. 0.1 12/11
PCI-Express Gen 1, Gen 2, &
Gen 3 Compliant
Low power push-pull type
differential output buffers
Integrated resistors on differential
clocks
Dedicated output enable
hardware pin for each clock
Hardware selectable spread
control
Four PCI-Express Clocks
Network attached storage
Multi-function printer
UTPUT
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
XIN/CLKIN
OE [3:0]
SDATA
SSON
XOUT
SCLK
XPRESS
Control & Memory
G
Control
E N E R A T O R
RAM
G
(SSC)
PLL
EN
Copyright © 2011 by Silicon Laboratories
1, G
25 MHz crystal input or clock
input
I
capabilities
Triangular spread spectrum
profile for maximum
electromagnetic interference
(EMI) reduction
Industrial temperature:
–40 to 85
3.3 V power supply
24-pin QFN package
Wireless access point
Routers
2
Divider
C support with readback
EN
o
C
2 , & G
DIFF1
DIFF3
DIFF0
DIFF2
EN
2
C
3 C
Patents pending
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
SSON
OE1
VDD
VSS
OE2
VDD
Ordering Information:
LOCK
1
2
1
1
2
3
4
5
6
Pin Assignments
S i 5 2 1 4 4
24
7
See page 18
23
8
22
9
GND
25
Q
21
10
20
11
UAD
12
19
18
17
16
15
14
13
OE3
VDD
DIFF3
DIFF3
DIFF2
DIFF2
Si52144
1

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SI52144 Summary of contents

Page 1

... Multi-function printer  Description The Si52144 is a spread-controlled PCIe clock generator that can source four PCIe clocks simultaneously. The device has four hardware output enable control inputs for enabling the respective differential outputs on the fly while powered on along with the spread control hardware pin to enable spread for EMI reduction ...

Page 2

... Si52144 2 Preliminary Rev. 0.1 ...

Page 3

... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. OE Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.3. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.4. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.5. SSON Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.1. Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5. Pin Descriptions: 24-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Preliminary Rev. 0.1 Si52144 Page 3 ...

Page 4

... Si52144 1. Electrical Specifications Table 1. DC Electrical Specifications Parameter Symbol 3.3 V Operating Voltage VDD core 3.3 V Input High Voltage 3.3 V Input Low Voltage Input High Voltage V Input Low Voltage V Input High Leakage Current Input Low Leakage Current 3.3 V Output High Voltage (SE) 3.3 V Output Low Voltage (SE) ...

Page 5

... Td=12 ns), High Band, 1.5 MHz < F < Nyquist Includes PLL BW 2–4 MHz, GEN3 CDR = 10 MHz) Measured differential ACC /T Measured differentially from R F ±150 mV HIGH LOW Preliminary Rev. 0.1 Si52144 Min Typ Max — — 250 47 — 53 and 0.5 — 4.0 DD — — 250 — ...

Page 6

... Si52144 Table 3. Absolute Maximum Conditions Parameter Main Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up. ...

Page 7

... Trim capacitors are calculated to provide equal capacitive loading on both sides. Table 4. Crystal Recommendations Shunt Motional Cap (max) (max) 12– 0.016 pF Figure 2. Crystal Loading Example Preliminary Rev. 0.1 Si52144 Tolerance Stability Aging (max) (max) (max) 35 ppm 30 ppm 5 ppm 7 ...

Page 8

... Si52144 Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side – (Cs + Ci) Total Capacitance (as seen by the crystal CLe ( 1 + Ce1 + Cs1 + Ci1 Ce2 + Cs2 + Ci2 CL: Crystal load capacitance  CLe: Actual loading seen by crystal using standard value trim capacitors  ...

Page 9

... Figure 3. 0.7 V Differential Load Configuration Figure 4. Differential Measurement for Differential Output Signals 0 0 (for AC Parameters Measurement) Preliminary Rev. 0.1 Si52144 ...

Page 10

... Si52144 V MIN Figure 5. Single-Ended Measurement for Differential Output Signals 10 = –0.30V V = –0.30V MIN (for AC Parameters Measurement) Preliminary Rev. 0.1 ...

Page 11

... Acknowledge from slave 37:30 Byte Count from slave—8 bits 38 Acknowledge 46:39 Data byte 1 from slave—8 bits 47 Acknowledge 55:48 Data byte 2 from slave—8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data Byte N from slave—8 bits .... NOT Acknowledge .... Stop Preliminary Rev. 0.1 Si52144 Description 11 ...

Page 12

... Si52144 Table 6. Byte Read and Byte Write Protocol Byte Write Protocol Bit Description 1 Start 8:2 Slave address–7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code–8 bits 19 Acknowledge from slave 27:20 Data byte–8 bits 28 Acknowledge from slave 29 Stop 12 Byte Read Protocol Bit ...

Page 13

... Bit D7 D6 Name R/W R/W Type Reset settings = 00000101 Bit Name 7:3 Reserved 2 DIFF0_OE Output Enable for DIFF0. 0: Output disabled. 1: Output enabled. 1 Reserved 0 DIFF1_OE Output Enable for DIFF1. 0: Output disabled. 1: Output enabled R/W R/W R/W Function R/W R/W R/W Function Preliminary Rev. 0.1 Si52144 R/W R/W R DIFF0_OE DIFF1_OE R/W R/W R/W 13 ...

Page 14

... Si52144 Register 2. Byte 2 Bit D7 D6 DIFF2_OE DIFF3_OE Name R/W R/W Type Reset settings = 11000000 Bit Name 7 DIFF2_OE Output Enable for DIFF2. 0: Output disabled. 1: Output enabled. 6 DIFF3_OE Output Enable for DIFF3. 0: Output disabled. 1: Output enabled. 5:0 Reserved Register 3. Byte 3 Bit D7 D6 Rev Code[3:0] Name R/W R/W Type ...

Page 15

... Reserved D5 R/W Function Amplitude Control for DIFF Differential Outputs. 0: Differential outputs with Default amplitude. 1: Differential outputs amplitude is set by Byte 5[6:4]. DIFF Differential Outputs Amplitude Adjustment. 000: 300 mV 001: 400 mV 010: 500 mV 100: 700 mV 101: 800 mV 110: 900 mV Preliminary Rev. 0.1 Si52144 R/W R/W R/W R/W R/W 011: 600 mV ...

Page 16

... Si52144 5. Pin Descriptions: 24-Pin QFN VDD OE1 2 SSON 3 4 VSS 1 5 OE2 VDD 6 Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. Table 7. Si52144 24-Pin QFN Descriptions Pin # Name Type PWR 3.3 V power supply 1,6 VDD I,PU 2 OE1 I,PD 3 SSON GND Ground 4 VSS I,PU 5 OE2 I,PU ...

Page 17

... Table 7. Si52144 24-Pin QFN Descriptions Pin # Name Type PWR 3.3 V power supply 12 VDD O, DIF 0.7 V, 100 MHz differential clock 13 DIFF2 O, DIF 0.7 V, 100 MHz differential clock 14 DIFF2 O, DIF 0.7 V, 100 MHz differential clock 15 DIFF3 O, DIF 0.7 V, 100 MHz differential clock 16 DIFF3 PWR 3.3 V power supply 17 VDD I,PU 18 OE3 ...

Page 18

... Si52144 6. Ordering Guide Part Number Lead-free Si52144-A01AGM Si52144-A01AGMR 18 Package Type 24-pin QFN 24-pin QFN—Tape and Reel Preliminary Rev. 0.1 Temperature Industrial, – C Industrial, – C ...

Page 19

... All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Millimeters Min Nom Max 0.70 0.75 0.80 0.00 0.025 0.05 0.20 0.25 0.30 4.00 BSC 2.60 2.70 2.80 0.50 BSC 4.00 BSC 2.60 2.70 2.80 0.30 0.40 0.50 0.10 0.10 0.08 0.07 Preliminary Rev. 0.1 Si52144 19 ...

Page 20

... Si52144 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...

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