com81c17 Standard Microsystems Corp., com81c17 Datasheet - Page 9

• Manufacturer Part Number: com81c17
• Description: Twenty Pin Uart Tpuart Corporation
• Manufacturer: Standard Microsystems Corp.

BIT
0
1
2
3
4
5
6
CP1 - This reflects the inverted state of the control pin CP1.
CP2 - This is active only when the nCP2 pin is programmed be to an input. It is set by its
corresponding input pin and reflects the inverted state of the control pin nCP2. When the
CP2 pin is programmed as an output, this bit is forced to a zero.
TX SHIFT REGISTER EMPTY - This signals the processor that the Transmit Shift
Register is empty. A typical program will usually load the last character of a transmission
and then monitor the TX SHIFT REGISTER EMPTY bit to determine when it is a safe
time for disabling transmission. This bit is set when the Transmitter Shift Register has
completed transmission of a character, and no new character has been loaded in the
Transmit Buffer Register. This bit is also set by asserting internal reset. This bit is
cleared by:
PARITY ERROR - This signals the processor that the character stored in the Receive
Character Buffer was received with an incorrect number of binary "1" bits. This bit is set
when the received character in the Receiver Buffer Register has an incorrect parity bit and
parity has been enabled. This bit is cleared by:
OVERRUN ERROR - This is set whenever a byte stored in the Receive Character Buffer
is overwritten with a new byte from the Receive Shift Register before being transferred to
the processor. This bit is cleared by:
FRAMING ERROR - This is set whenever a byte in the Receive Character Buffer was
received with an incorrect bit format ("0" stop bits). This bit is cleared by:
TX BUFFER EMPTY - This signals the processor that the Transmit Buffer Register is
empty and that the TPUART can accept a new character for transmission. This bit is set
when:
This bit is cleared by:
This bit is initially set when the transmitter logic is enabled by setting the TX Enable bit in
the Control Register (also TX Buffer is empty because of reset). Data can be overwritten
if a consecutive write is performed while TX Buffer Empty is zero.
A)
A)
B)
A)
B)
A)
B)
A)
B)
C)
A)
Table 4 - COM81C17 Status Registers Description (Bits 0-7)
Loading the TX Buffer Register
Setting Reset Errors in the Control Register
Asserting internal reset
Setting Reset Errors in the Control Register
Asserting internal reset
Setting Reset Errors in the Control Register
Asserting internal reset
A character has been loaded from the Transmit Buffer Register to the Transmit
Shift Register
Asserting the TRANSMIT RESET bit in the Control Register
Asserting internal reset
Writing to the Transmit Buffer Register
DESCRIPTION
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