bt848kpf ETC-unknow, bt848kpf Datasheet - Page 64

• Manufacturer Part Number: bt848kpf
• Description: Single-chip Video Capture For Pci
• Manufacturer: ETC-unknow

F
DMA Controller
54
UNCTIONAL
D
ESCRIPTION
relay information such as the opcode, target address, status codes, synchronization
codes, byte count/enables, and start/end of line codes.
struction is the first instruction of the scan line. The EOL bit in the WRITE and
SKIP instructions indicate that this particular instruction is the last instruction of
the scan line. An EOL flag from the FIFO along with the last DWORD for the scan
line coincide with finishing the last instruction of the scan line. If the FIFO EOL
condition occurs early, then the current instruction and all instructions leading up
to the one that contains the EOL flag are aborted. If there is only one instruction to
process the line, both SOL and EOL bits will be set.
in the FIFO. These three instructions alone control the sequence of packed mode
data written to target memory on a byte resolution basis. The WRITEC instruction
does not supply a target address. Instead, it relies on continuing from the current
DMA pointer contained in the target address counter. This value is updated and
kept current even during SKIP mode or FIFO overruns. However, WRITEC cannot
be used to begin a new line, i.e. this instruction cannot have the SOL bit set.
data stored in the FIFOs. These three instructions alone control the sequence of
planar mode data written to target memory on a byte resolution basis. The
WRITE1S23 instruction supports further decimation of chroma on a line basis. For
each of these instructions, the same number of bytes will be processed from FIFO2
and FIFO3.
ery frame or switching to a new program when the sequence needs to be changed
without interrupting the pixel flow.
data stream. The DMA controller achieves this through the use of the status bits in
DWORD0 of the SYNC instruction, and by matching them to the four FIFO status
bits provided along with the pixel data. Once the DMA controller has matched the
status bits between the FIFO and the RISC instruction, it proceeds with outputting
data. Prior to establishing synchronization, the DMA controller reads and discards
the FIFO data.
codes or the other unused opcodes are detected, an interrupt will be set. The DMA
Controller will stop processing until the RISC program is re-enabled. This also ap-
plies to SYNC instructions specifying unused or reserved status codes. Detecting
RISC instruction errors is useful for detecting software errors in programming, or
ensuring that the DMA Controller is following a valid RISC sequence. In other
words, it ensures that the program counter is not pointing to the wrong location.
Each RISC instruction consists of 1 to 5 DWORDs. The 32 bits in the DWORDs
The SOL bit in the WRITE and SKIP instructions indicate that this particular in-
WRITE, WRITEC and SKIP control the processing of active pixel data stored
WRITE123, WRITE1S23, and SKIP123 control the processing of active pixel
The JUMP instruction is useful for repeating the same even/odd program for ev-
The SYNC instruction is used to synchronize the RISC program and the pixel
Opcodes 0000 and 1111 are reserved to detect instruction errors. If these op-
All unused/reserved bits in the instruction DWORDs must be set to zero.
L848A_A
Single-Chip Video Capture for PCI
Bt848/848A/849A
Brooktree
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