at1240 Arrive Technologies, Inc., at1240 Datasheet
at1240
Manufacturer Part Number
at1240
Description
Oc-12/3 Ethernet Over Pdh/sonet Mapper Lite
Manufacturer
Arrive Technologies, Inc.
Datasheet
1.AT1240.pdf
(2 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
at1240DN-5.0TRG1
Manufacturer:
BCD
Quantity:
45 015
G
The AT1240 provides a multi-format and multi-rate Ethernet and common legacy data over PDH, PDH mapped to SONET/SDH or direct SONET
mapping. On the PDH side, the chip provides a parallel multiplexed PDH bus carrying 3 DS3s or 3 E3s or 84 DS1s or 63 E1s or any mixture of
them. A simple FPGA is used to convert parallel DS1/E1/DS3/E3 signals on the PDH bus to the serial signals required for the LIUs for pin count
expansion. The 84DS1/63E1s signals can be accessed directly on the PDH bus or be multiplexed to 3 channelized DS3/E3s via 3 embedded
M13/E13 engines or mapped to SONET/SDH. The chip supports a quad OC-12/STM-4/OC-3/STM-1 SONET/SDH interface with 1+1 protection,
UPSR and mapping of DS1/E1/DS3/E3 to SONET/SDH. On the Ethernet side, the chip provides 8 Fast Ethernets via SMII/SS-SMII bus and 2
Gigabit Ethernet ports with on-chip CDRs. It also supports an OIF SPI-3 bus to support external devices such as a Packet Switches, Network
Processor to provide extended L2+ or L3 level processing or expansion of the Ethernet ports. The AT1240 supports ATM, GFP-T/F, HDLC, PPP
and LAPS encapsulation. A Traffic Aggregation and Management at Layer 2 for VLAN/MPLS with Classifying, Policing, Queuing, Shaping, and
Scheduling is provided. It provides direct SONET/SDH mapping, SONET/SDH/PDH virtual concatenation (VCAT) and LCAS with 128 groups in
accordance with G.7041, G.8040, G.7042 and G.7043. The AT1240 includes flexible channel assignment for all applicable SDH and SONET
mappings. A serial port is provided for ESCON, DVB-ASI or low speed Fiber Channel SAN applications.
K
A
A
US
© 2007 Arrive Technologies All Rights Reserved
G
K
A
A
E
P
T
STM‐4/ OC‐
E
E
P
T
E
PDH Bus
3/ STM‐1
OC‐12/
84 DS1
Quad
63 E1
3 DS3
1
1
UPSR
Y
Y
P
P
3 E3
N
1+1
N
2
2
L
L
E
E
F
F
4
4
Eight 10/100Mpbs Ethernet ports via SMII/SS-SMII
One 1Gbps Ethernet ports with on-chip CDR
One ESCON/DVB-ASI/Low Speed FC (200/270/531Mbps)
128 Logical ports SPI-3 interface for Ethernet expansion
Quad multi-rate OC-12/STM-4/OC-3/STM-1 ports with
3 DS3/E3s, or 84 DS1s, or 63 E1s or any mixture of them
Ethernet MAC controller with flow control including jumbo
Support 802.3ah Ethernet OAM processing and loopback
128 Hi/Lo-Order/PDH VCAT channels with external memory
supported delay compensation and on-the-fly programmable
differential delays for each VCAT channel
Each VCAT channel supports differential delay with up to
LCAS with hitless add/remove and fault isolation
Carrier Ethernet wireless and business aggregation and
backhaul systems
Customer Premises Data Service aggregation and
multiplexers
Routers, Switches, Edge Systems, MSPPs and Broadband
DLCs
NxDS1/E1 carrying packet data from mobile backhaul base
stations to transport network
NxDS1/E1 over DS3/E3 M13/E13 carrying packet data from
mobile backhaul base stations to transport network
NxDS3/E3 carrying packet data from Business or Enterprise
w
I
port with serial clock and data interface
on-chip CDR
on a multiplexed PDH bus
frame
384ms for DS1s, up to 256ms for E1/E3s and up to 217ms
for DS3s, up to 256ms of STS/VC/VT/TU
I
to transport network
R
R
E
C
E
C
0
0
Per DSn/En
A
A
A
A
A
A
B
B
Redundancy
4 OC‐12/3/
Clock Sync
L
L
T
T
T
T
STM‐4/1
w
Framers
L
L
U
U
I
I
D
D
O
O
A
OC-12/3 Ethernet over PDH/SONET Mapper Lite
Rev. 1.3 – May 2008
O
A
O
R
R
E
E
C
C
N
N
T
T
w
E
E
S
JTAG
S
K
K
S
1
S
1
S
S
C
C
2
2
D
D
Controller
Data Link
R
R
.
STS/AU
Pointer
4
4
I
I
I
A
I
A
0
0
P
P
511-channel
G
G
T
a
T
POH
R
R
I
I
O
O
A
A
DS3/E3 Map
STS/AU/
r
N
TU3 XC
N
M
M
Microprocessor
3
uP Interface
r
Framers
DS3/E3
Bus
3
i
Pointer
VT/TU
v
M13/
ZBT RAM
Interface
E13
ZBT SRAM
3
Interface
DS1/E1 Map
e
84/63
VT/TU
XC
Framers
DS1/E1
84/63
t
e
SDRAM Interface
c
VCAT DDR2
128‐VCG
Order/
VCAT/
Hi/Lo‐
LCAS
MAP
PDH
h
84 DS1/J1
63 E1
3 DS3/E3
STM‐4/ OC‐
UPSR,1+1
3/ STM‐1
OC‐12/
Quad
n
channel
sulation
Encap‐
HDLC
o
GFP-F/T, PPP/HDLC, LAPS and ATM encapsulation
Traffic Aggregation and Management at Layer 2 for
Eliminates an external packet SDRAM for transportation of
3 DS3 C-bit Parity and DS3 M13 multiplexing
3 E3 G.832 and E3 G.751 E13 multiplexing
84 DS1 SF/ESF Framers supporting J1 SF/ESF
63 E1 basic frame or CRC-4 multi-frame framers
Mapping of 84DS1/63E1 and 12DS2/E3 to SONET/SDH
2x16Mx16 DDR2 SDRAM for VCAT delay compensation
3x16Mx16 DDR2 SDRAM for Data Aggregation buffer (can
1x512Kx36 ZBT SSRAM for hardware status.
Provided in an HFC-BGA1296 package
Typical power consumption is 5 watts
LAPS
128‐
ATM
VLAN/MPLS with Classifying, Policing, Queuing, Shaping,
and Scheduling
Ethernet ports over PDH without statistical multiplexing
(can be eliminated if VCAT is not utilized)
be eliminated if Data Aggregation is not utilized)
GFP
SONET/SDH
PPP
LIUs
(DDR2 SDRAM for Agg. eliminated)
SFP
l
[96:103]
Bypassing Data Agg.
[0:95]
[104:127]
Interface
o
PDH
FPGA
SONET/SDH CDR
Interface
GFP‐T
g
[96:103]
PDH
Bus
i
1GE + 6FE
e
SDRAMs
DDR2
AGG DDR2 SDRAM Interface (N/A
[96:127]
A
A
VCGs
A
A
32
in Data Agg. Bypass mode)
s
T
m
m
T
1
a
1
a
Preliminary Short Data Sheet
l
256‐flow
l
2
2
t
t
h
.
h
Data
Agg.
4
4
SSRAM
e
e
ZBT
0
0
a
a
c
[96:127]
o
Interface
GbE CDR
Ethernet
SS‐SMII
128‐port
SMII/
SPI‐3
SAN
MAC
SPI
m
Expansion
Interface
Ethernet
Ethernet
SAN
PHY
PHY
GbE
SFP
VIETNAM
Low Speed
SPI-3
1 ESCON/
1 GbE
DVB-ASI/
8 FEs
FC
Page 1
1Gb Ethernet
10/100/1000
8x10/100
Ethernet
Ethernet
DVB‐ASI
ESCON
LS FC
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at1240 Summary of contents
Page 1
... Gigabit Ethernet ports with on-chip CDRs. It also supports an OIF SPI-3 bus to support external devices such as a Packet Switches, Network Processor to provide extended L2 level processing or expansion of the Ethernet ports. The AT1240 supports ATM, GFP-T/F, HDLC, PPP and LAPS encapsulation. A Traffic Aggregation and Management at Layer 2 for VLAN/MPLS with Classifying, Policing, Queuing, Shaping, and Scheduling is provided ...
Page 2
OC-12/3 Ethernet over PDH/SONET Mapper Lite Rev. 1.3 – May 2008 ...