at1250 Arrive Technologies, Inc., at1250 Datasheet
at1250
Manufacturer Part Number
at1250
Description
Oc-12/3 Ethernet Over Pdh/sonet Mapper
Manufacturer
Arrive Technologies, Inc.
Datasheet
1.AT1250.pdf
(3 pages)
G
The AT1250 provides a multi-format and multi-rate Ethernet and common legacy data over PDH, PDH mapped to SONET/SDH or direct SONET
mapping. On the PDH side, the chip provides a parallel multiplexed PDH bus carrying 12 DS3s or 12 E3s or 336 DS1s or 252 E1s or any mixture
of them. A simple FPGA is used to convert parallel DS1/E1/DS3/E3 signals on the PDH bus to the serial signals required for the LIUs for pin
count expansion. The 336DS1/252E1s signals can be accessed directly on the PDH bus or be multiplexed to 12 channelized DS3/E3s via 12
embedded M13/E13 engines or mapped to SONET/SDH. The chip supports a quad OC-12/STM-4/OC-3/STM-1 SONET/SDH interface with 1+1
protection, UPSR and mapping of DS1/E1/DS3/E3 to SONET/SDH. On the Ethernet side, the chip provides 8 Fast Ethernets via SMII/SS-SMII
bus and 2 Gigabit Ethernet ports with on-chip CDRs. It also supports an OIF SPI-3 bus to support external devices such as a Packet Switches,
Network Processor to provide extended L2+ or L3 level processing or expansion of the Ethernet ports. The AT1250 supports ATM, GFP-T/F,
HDLC, PPP and LAPS encapsulation. A Traffic Aggregation and Management at Layer 2 for VLAN/MPLS with Classifying, Policing, Queuing,
Shaping, and Scheduling is provided. It provides direct SONET/SDH mapping, SONET/SDH/PDH virtual concatenation (VCAT) and LCAS with
128 groups in accordance with G.7041, G.8040, G.7042 and G.7043. The AT1250 includes flexible channel assignment for all applicable SDH
and SONET mappings. A serial port is provided for ESCON, DVB-ASI or low speed Fiber Channel SAN applications.
K
A
A
US
© 2008 Arrive Technologies All Rights Reserved
G
K
A
A
PDH Bus
336 DS1
E
P
T
STM‐4/
E
E
P
T
OC‐12/
12 DS3
E
STM‐1
252 E1
OC‐3/
Quad
UPSR
12 E3
1+1
1
1
Y
Y
P
P
N
N
2
2
L
L
E
E
F
F
5
5
Eight 10/100Mpbs Ethernet ports via SMII/SS-SMII
Two 1Gbps Ethernet ports with on-chip CDR
One ESCON/DVB-ASI/Low Speed FC (200/270/531Mbps)
128 Logical ports SPI-3 interface for Ethernet expansion
Quad multi-rate OC-12/STM-4/OC-3/STM-1 ports with
12 DS3/E3s, or 336 DS1s, or 252 E1s or any mixture of them
Ethernet MAC controller with flow control including jumbo
Support 802.3ah Ethernet OAM processing and loopback
128 Hi/Lo-Order/PDH VCAT channels with external memory
Each VCAT channel supports differential delay with up to
Carrier Ethernet wireless and business aggregation and
backhaul systems
Customer Premises Data Service aggregation and
multiplexers
Routers, Switches, Edge Systems, MSPPs and Broadband
NxDS1/E1 carrying packet data from mobile backhaul base
NxDS1/E1 over DS3/E3 M13/E13 carrying packet data from
NxDS3/E3 carrying packet data from Business or Enterprise
w
I
port with serial clock and data interface
on-chip CDR
on a multiplexed PDH bus
frame
supported delay compensation and on-the-fly programmable
differential delays for each VCAT channel
384ms for DS1s, up to 256ms for E1/E3s and up to 217ms
for DS3s, up to 256ms of STS/VC/VT/TU
I
DLCs
stations to transport network
mobile backhaul base stations to transport network
to transport network
R
R
E
C
E
C
0
Per DSn/En
0
A
A
A
A
A
A
Redundancy
B
B
4 OC‐12/3/
Clock Sync
STM‐4/1
Framers
L
L
T
T
T
T
w
L
L
U
U
I
I
D
D
O
O
A
OC-12/3 Ethernet over PDH/SONET Mapper
Rev. 1.4 – May 2008
O
A
O
R
R
E
E
C
C
N
N
T
T
w
JTAG
E
E
S
S
K
K
S
1
S
1
S
S
C
C
Controller
2
2
Data Link
D
D
STS/AU
Pointer
R
R
.
5
5
I
I
I
A
511‐channel
I
A
0
0
P
P
G
G
POH
T
a
T
R
R
I
I
O
O
DS3/E3 Map
A
A
STS/AU/
TU3 XC
r
N
N
M
M
12
Microprocessor
Interface
r
Framers
DS3/E3
Bus
uP
12
Pointer
i
VT/TU
v
M13/
ZBT RAM
Interface
E13
12
ZBT SRAM
Interface
DS1/E1 Map
336/252
e
VT/TU
XC
336/252
Framers
DS1/E1
t
e
VCAT DDR2 SDRAM
c
LCAS MAP
128‐VCG
Order/
Interface
Hi/Lo‐
VCAT/
PDH
336 DS1/J1
252 E1
12 DS3/E3
h
UPSR,1+1
OC-12/
STM-4/
STM-1
Quad
OC-3/
n
channel
sulation
Encap‐
o
LCAS with hitless add/remove and fault isolation
GFP-F/T, PPP/HDLC, LAPS and ATM encapsulation
Traffic Aggregation and Management at Layer 2 for
Eliminates an external packet SDRAM for transportation of
12 DS3 C-bit Parity and DS3 M13 multiplexing
12 E3 G.832 and E3 G.751 E13 multiplexing
336 DS1 SF/ESF Framers supporting J1 SF/ESF
252 E1 basic frame or CRC-4 multi-frame framers
Mapping of 336DS1/252E1 and 12DS2/E3 to SONET/SDH
2x16Mx16 DDR2 SDRAM for VCAT delay compensation
3x32Mx16 DDR2 SDRAM for Data Aggregation buffer (can
1x512Kx36 ZBT SSRAM for hardware status
Provided in an HFC-BGA1296 package
Typical power consumption is 5 watts
SONET/SDH
HDLC
VLAN/MPLS with Classifying, Policing, Queuing, Shaping,
and Scheduling
Ethernet ports over PDH without statistical multiplexing
(can be eliminated if VCAT is not utilized)
be eliminated if Data Aggregation is not utilized)
LAPS
ATM
128‐
LIUs
GFP
PPP
(DDR2 SDRAM for Agg. eliminated)
SFP
l
[96:103]
Bypassing Data Agg.
[0:95]
[104:127]
Interface
o
FPGA
PDH
CDR Interface
SONET/SDH
g
GFP‐T
[96:103]
PDH
Bus
i
e
1GE + 6FE
SDRAMs
DDR2
[96:127]
AGG DDR2 SDRAM Interface (N/A in
A
G
G
A
VCGs
s
32
a
a
T
T
n
n
Data Agg. Bypass mode)
1
y
Preliminary Short Data Sheet
1
y
m
m
256‐flow
2
2
.
Data
e
e
SSRAM
Agg.
5
5
d
ZBT
d
0
0
e
e
c
o
[96:127]
GbE CDR
SS-SMII
Interface
SMII/
SPI-3
128‐port
Ethernet
SAN
m
MAC
SPI
Expansion
Interface
Ethernet
Ethernet
SAN
PHY
PHY
GbE
SFP
VIETNAM
Low Speed
SPI‐3
2 GbEs
1 ESCON/
DVB‐ASI/
8 FEs
Page 1
FC
10/100/1000
8x10/100
DVB-ASI
Ethernet
Ethernet
Ethernet
ESCON
LS FC
2x1Gb
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at1250 Summary of contents
Page 1
... O N The AT1250 provides a multi-format and multi-rate Ethernet and common legacy data over PDH, PDH mapped to SONET/SDH or direct SONET mapping. On the PDH side, the chip provides a parallel multiplexed PDH bus carrying 12 DS3s or 12 E3s or 336 DS1s or 252 E1s or any mixture of them. A simple FPGA is used to convert parallel DS1/E1/DS3/E3 signals on the PDH bus to the serial signals required for the LIUs for pin count expansion ...
Page 2
OC-12/3 Ethernet over PDH/SONET Mapper Rev. 1.4 – May 2008 ...
Page 3
OC-12/3 Ethernet over PDH/SONET Mapper Rev. 1.4 – May 2008 10Mbps redundancy data link Active/standby switchover under software control © ...