sii141b ETC-unknow, sii141b Datasheet
sii141b
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sii141b Summary of contents
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... Channel 1 Data 1-pixel/clock 18-bit Even Data for 2-pixel/clock mode 6-bit Even Channel 2 6-bit Even Channel 1 Data 2-pixel/clock Data 2-pixel/clock SiI141B 80-Pin TQFP (Top View) DIFFERENTIAL SIGNAL May 2001 Scaleable Bandwidth: 25-86 MHz (VGA to High Refresh XGA) Low Power: 3.3V core operation & power-down mode ...
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Functional Block Diagram ST PIXS DFO OCK_INV PDO HSYNC_DEJTR Termination EXT_RES Control RX2+ VCR RX2- RX1+ VCR RX1- RX0+ VCR RX0- RXC+ VCR RXC- Absolute Maximum Conditions Note: Permanent device damage may occur if absolute maximum conditions are exceeded. Functional ...
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DC Specifications Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are shown in brackets. Symbol I Output High Drive OHD Data and Controls I Output Low Drive OLD Data and Controls I ODCK High Drive ...
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AC Specifications Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are given below. Symbol Parameter T Intra-Pair (+ to -) Differential Input Skew DPS T Channel to Channel Differential Input Skew CCS T Worst Case ...
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... Timing Diagrams SiI141B 2.0 V RX0 DIFF RX1 T CCS RX2 Output Timing ODCK_INV = 1 ODCK_INV = 0 QE[23:0]/QO[23:0], DE, VSYNC, HSYNC, CTL[3:1] Silicon Image, Inc. SiI 141B 2.0 V 10pF (5pF) 0 LHT Figure 1. Digital Output Transition Times R CIP R CIH 2 CIL Figure 2. Receiver Clock Cycle/High/Low Times DIFF Figure 3 ...
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PD Q[35:0], DE, VSYNC, HSYNC, CTL[3:1] Figure 5. Output Signals Disabled Timing from PD Active RXC Q[35:0], DE, VSYNC, HSYNC, CTL[3:1] Figure 6. Output Signals Disabled Timing from Clock Inactive RXC SCDT DE SCDT DE SCDT Silicon Image, Inc. SiI ...
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Output Pin Description Pin Name Pin # Type Description Q35 – Q0 See Out Output Data [35:0]. Output data is synchronized with output data clock (ODCK). SiI 141B Pin When PIXS is low Q35-Q24 are low and Q23-Q0 output 24-bit/pixel ...
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... CLK delays in the HSYNC signal relative to the output data. The SiI141B includes a new power saving feature, power down with clock detect circuit. The SiI141B will go into a low power mode when there is no video clock coming from the transmitter. In this mode the entire chip is powered down except the clock detect circuitry ...
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... The calculation for the maximum resistor value is shown in the equation [1] below. In powered down mode, low power consumption is achieved by making the resistor value as large as possible. Equation [1] determines the maximum value of R while ensuring that SCDT stays lower than V impedance. The small current flowing into the SiI141B internal pull down resistor is ignored in equation [1]. Equation [1a] R ...
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R Equation [2] Example : When ST(pin# 79) = 1,Vcc = 3.3V R > 660 = Vcc ( external chip) / Min I IH The resistor value should be larger than 660ohms When ST(pin# 79) = 0,Vcc = ...
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... Lead Pitch 0.50mm Device # Lot # Date Code # SiI Rev. # Package Height Clearance 1.15mm max. 0.15mm max. Silicon Image, Inc. SiI 141B 80-pin Plastic TQFP SiI141BCT80 LNNNNN.NLLL XXYY X.XX Body Size 12.00mm Footprint 14.00mm 11 SiI-DS-0037-C Body Thickness 1.0mm Subject to Change without Notice ...
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... Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Ordering Information Part Number: SiI141BCT80 Revision History Revision Date ...