ax88140a ETC-unknow, ax88140a Datasheet
ax88140a
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ax88140a Summary of contents
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... No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. ASIX ELECTRONICS CORPORATION 2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. TEL: 886-3-579-9500 Fast Ethernet MAC Controller ASIX AX88140A Data Sheet(11/03/’97) FAX: 886-3-579-9558 AX88140A DOCUMENT NO. : AX140D2.DOC ...
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... AX88140A 1.0 INTRODUCTION ................................................................................................................................................ 6 1 ...................................................................................................................................... 6 ENERAL ESCRIPTION 1.2 F ............................................................................................................................................................ 7 EATURES 1 ............................................................................................................................................... 8 LOCK IAGRAM 1.4 AX88140AQ ONNECTION 1.5 AX88140AP ONNECTION 2.0 SIGNAL DESCRIPTION .................................................................................................................................. 11 2 160- IGNAL ESCRIPTIONS FOR 2.2 PCI ...................................................................................................................................... 12 INTERFACE GROUP 2.3 B ROM , S ROM , G OOT ERIAL 2.4 MII/SYM/SRL INTERFACE SIGNALS GROUP 2 NC, P XTENDED OWER PINS GROUP 3.0 CONFIGURATION OPERATION .................................................................................................................. 17 3 ...
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... PPLICATION FOR OOT B ROM I PPLICATION FOR ERIAL B.4 A PHY I PPLICATION FOR NTERFACE B.4.1 AX88140A, QSI6611, & MTD213 Application ......................................................................................... 45 B.4.2 Application for MII Mode : LEVEL ONE LXT970.................................................................................... 45 B.4.3 Application for MII Mode : MYSON MTD972 + MTD971....................................................................... 46 B.4.4 Application for MII Mode : DAVICOM DM9101 ..................................................................................... 46 ........................................................................................................................ 35 ................................................................................................................... 35 ........................................................................................................................ 36 ............................................................................................................................ 42 .................................................................................................................... 43 ....................................................................................................... 44 NTERFACE ...
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... AX88140A AX88140A LOCK IAGRAM AX88140AQ CONNECTION DIAGRAM FOR AX88140AP CONNECTION DIAGRAM FOR ESCRIPTOR TRUCTURE XAMPLE ECEIVE ESCRIPTOR ORMAT RANSMIT ESCRIPTOR ORMAT PCS / S IG PPLICATION FOR ...
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... AX88140A PCI ................................................................................................................................... 13 AB INTERFACE GROUP ROM , S ROM , G AB OOT ERIAL MII/SYM/SRL AB INTERFACE SIGNALS GROUP NC XTENDED OWER PINS GROUP ONFIGURATION PACE APPING CSID ONFIGURATION CSCS OMMAND AND TATUS ...
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... It implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 LAN standard. l The AX88140A contains a high speed 32 bit PCI Bus master interface to host CPU. Two large independent transmit and receive FIFO allow the AX88140A to buffer the Ethernet packet efficiently. l The 10/100Mbps ports can be programmed to support 10Mbps, 100Mbps media-independent interface (MII), or 100BASE-TX physical coding sub-layer (PCS)mode, For 10Mbps operation AX88140A provides a standard serial Interface to the external 10Mbps ENDEC chip ...
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... AX88140A 1.2 Features l Single chip PCI bus Fast Ethernet Controller. l Direct interface to PCI bus. l Support both 10Mbps and 100Mbps data rate. l Full or Half duplex operation supported for both10Mbps and 100Mbps operation. l Provides a MII port for both 10/100Mbps operation chip PCS support for 100BASE-TX symbol mode operation. ...
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... BUS Interface BOOT ROM Interface Serial BOOT ROM I/F Receive FIFO MAC Buffer Management Controller DMA Engine Transmit FIFO General Purpose REG General purpose I/O pins Fig - 1 AX88140A Block Diagram 8 PRELIMINARY MII MII Interface PCS SYM Interface 10 BT Interface SRL ASIX ELECTRONICS CORPORATION ...
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... AX88140A 1.4 AX88140AQ Pin Connection Diagram for 160-pin The AX88140A is housed in the 160-pin plastic quad flat pack. pin connection diagram int# 4 rst# 5 vdd 6 vss 7 pci_clk 8 vdd gnt req vss ad<31> ad<30> vss ad<29> ad<28> vss 1 8 ad< ...
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... AX88140A 1.5 AX88140AP Pin Connection Diagram for 144-pin The AX88140A is housed in the 144-pin plastic quad flat pack. pin connection diagram. int# 1 rst# 2 vdd 3 vss 4 pci_clk 5 vdd 6 gnt# 7 req# 8 vss 9 ad<31> ad<30> vss 1 2 ad<29> ad<28> vss 1 5 ad<27> ad<26> vdd 1 8 ad<25> ad<24> ...
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... AX88140A 2.0 Signal Description 2.1 Signal Descriptions for 160-pin and 144-pin The following terms describe the AX88140A pin-out: l Address phase Address and appropriate bus commands are driven during this cycle. l Data phase Data and the appropriate byte enable codes are driven during this cycle. ...
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... While FRAME# is asserted, data transfers continue. When FRAME# deasserts the next data phase is the final data phase transaction. 7 BUS GRANT Indicates to the AX88140A That access to the bus is granted. 22 Initialization devise select asserts To indicate that the host is issuing a configuration cycle to the AX88140A ...
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... Parity error asserts when a data parity error is detected. When the AX88140A is the bus master it monitor PERR# to see if the target report a data parity error., when the AX88140A is the bus target and a parity error is detected, the AX88140A asserts PERR#. This pin must be pulled external resistor. ...
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... MII management data clock is sourced by the AX88140A to the PHY devices as a timing reference for the transfer of information on the MII_MDIO signal. 115 105 MII management data input/output transfers control information and status between the PHY and the AX88140A ...
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... SRL_RCLK signal. 150 136 Receive enable signals activity on the Ethernet cable to the AX88140A asserted when receive data is present on the Ethernet cable and is deasserted at the end of a frame. It may be asserted and deasserted asynchronously to the receive clock (SRL_RCLK) by the external ENDEC. ...
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... AX88140A 2.5 Extended , NC, Power pins group SIGNAL TYPE PIN NUMBER FOR 160 PIN EC<15:0> O 160,159,122, 121,120,119, 82,81,80,79,42,41 ,40,39,2 114,138,155,156, 157,158 VDD P 5,8,20,30,33, 50,62,73,85, 95,108,117, 135,143 VDD VSS P 6,11,14,17,25, 34,35,38,43, 55,59,65,70, 76,84,94,100, 107,118,134, 142 Tab - 4 Extended , NC, Power pins group PIN DESCRIPTION NUMBER FOR 144 PIN NONE Expended pins. do not connect. ...
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... AX88140A 3.0 Configuration Operation 1. Software reset (REG0<0>) has no effect on the configuration registers. 2. Hardware reset puts the configuration registers in default values. 3. The configuration registers could be accessed in byte, word , and long-word. 3.1 Configuration Space Mapping CONFIGURATION REGISTER DEVICE/VENDOR ID COMMAND AND STATUS REVISION LATENCY TIMER BASE I/O ADDRESS ...
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... Subclass : Always equal to 0H that indicates the fast Ethernet controller 7:4 R Revision Number : Indicates the AX88140A revision number and is equal to 0H 3:0 R Step Number : Indicates the AX88140A step number and is referred to current silicon step. Tab - 8 CSRV Configuration Revision Register Description 3.2.4 Configuration Latency Timer Register (CSLT) FIELD R/W 31:16 ...
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... MAX_LAT : time unit is equal to 0.25 microsecond.(28H) 23:16 R MIN_GNT : Time unit is equal to 0.25 microsecond.(14H) 15:8 R Interrupt Pin : The AX88140A uses INTA# and the read value is (01H). 7:0 R/W Interrupt Line : The BIOS writes the routing information into this field. Tab - 13 CSIT Configuration Interrupt Register Description PRELIMINARY ...
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... AX88140A 4.0 Registers Operation 1. The REGs are quad-word aligned, 32-bits long, and must be accessed using long-word instruction with quad-word aligned addresses only. 2. Reserved bits should be written with 0.; Reserved bits are UNPREDICTABLE on read access. 3. Retries on second data transactions occur in response to burst accesses. 4.1 Registers Mapping ...
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... PBL - Programmable Burst Length Indicates the maximum number of longwords to be transfered in one DMA transaction. If reset, the ax88140a burst is limited only by the amount of data stored in the receive FIFO (at least 16 longword the amount of free space in the transmit FIFO (at least 16 longword) before issuing a bus request. ...
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... Tab - 18 REG3 Receive List Base Address Register Description 4.2.5 Transmit List Base Address (REG4) 1. The register is used to point the AX88140A to the start of transmit descriptors list. 2. The descriptor list resides in physical memory space and must be long-word aligned. The AX88140A behaves UNPREDICTABLY when the list are not long-word aligned. ...
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... AX88140A 4.2.6 Status Register (REG5) 1. The status register contains all the status bits that the AX88140A reports to the host. 2. Most of the fields in this register cause the host to be interrupted. 3. REG5 bits are not cleared when read. 4. Writing 1 to these bits clears them; writing 0 has no effect. Each field can be masked. ...
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... R Threshold Control Bits The threshold value has a direct impact on the AX88140A bus arbitration scheme . Transmission starts when the frame size within the transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. The transmit process must be in the stopped state to change these bits ...
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... AX88140A 8 R Receive broadcast packet 7 R Pass All Multicast 6 R Promiscuous Mode 5:4 - Reserved.--Written as “0” for future compatibility concern Pass Bad Frames 2 - Reserved.--Written as “0” for future compatibility concern Start/Stop Receive 0 R PLS - PCS_SYM Link Status : Active high. ...
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... AX88140A 4.2.8 Interrupt Enable Register (REG7) 1. The interrupt enable register (REG7) enables the interrupts reported by REG5. 2. Setting bit to 1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled. Field R/W/C 31:17 - Reserved 16 R Normal Interrupt Summary Enable When set, normal interrupt is enabled. ...
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... MII management data clock (MII_MDC output signal to the PHY used as a timing reference Read operation Read control bit. When set together with REG9<12>, The AX88140A performs read cycles from the BOOT ROM, and the serial ROM. 13:12 - Reserved.--Written as “0” for future compatibility concern. ...
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... Tab - 29 REG14 Filtering Data Register Description Filtering Buffer The AX88140A stores one Ethernet address for local physical address and filters the packets with multicast addresses by 64 bits array. For any incoming frame with a multicast destination address, the AX88140A applies the standard Ethernet cyclic redundancy check function to the destination address, then uses the most significant 6 bits of the result as a bit index into the table ...
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... AX88140A 1 RESERVED MULTICAST 2 ADDRESS FILTERING TABLE FILTERING TABLE BIT multicast address 3 filtering table bit 56 - filtering table bit Tab - 31 Layout of Filtering Buffer RESERVED PHYSICAL ADDRESS BYTE 5 MULTICAST MULTICAST ADDRESS ADDRESS FILTERING TABLE BIT BIT multicast address multicast address filtering ...
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... Descriptor Lists and Data Buffers The AX88140A transfers data frames to the receive buffers and from the transmit buffers in host memory. Descriptors that reside in the host memory act as pointers to these buffers. There are two descriptor lists, one for receive and one for transmit. The base address of each list is written into REG3 and REG4, respectively ...
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... RDES0 contains the received frame status, the frame length, and the descriptor ownership information. Field 31 OWN - Own Bit The AX88140A clears this bit either when it completes the frame reception or when the buffers that are associated with this descriptor are full Filtering Fail This bit can be set only when receive all (REG6< ...
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... FIELD 31:11 Reserved.--Written as “0” for future compatibility concern. 10:0 RBS - Receive Data Buffer Size Indicates the size in bytes of the data buffer. If this field is 0, the AX88140A ignores this buffer. The buffer size must be a multiple of 4. 5.2.3 Receive Descriptor 2 (RDES2) FIELD 31:0 Data Buffer Pointer Indicates the physical address of data buffer. The buffer must be long-word-aligned (RDES2< ...
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... This bit is effective only in 10Mb/s operation mode. When set, indicates a heartbeat collision check failure This bit is not valid if under-flow error (TDES0<1>) is set. On the second transmission attempt, after the first transmission was aborted due to collision, the AX88140A does not check heartbeat fail and (TDES0<7>) is reset. ...
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... Reserved.--Written as “0” for future compatibility concern Add CRC Disable When set, the AX88140A does not append the CRC to the end of the transmitted frame. This field is valid only when first segment (TDES1<29>) is set. 25:24 Reserved.--Written as “0” for future compatibility concern. ...
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... AX88140A 6.0 Electrical Specification and Timings 6.1 Absolute Maximum Ratings Description Operating Temperature Storage Temperature Supply Voltage Input Voltage Output Voltage Lead Temperature (soldering 10 seconds maximum) Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability 6 ...
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... AX88140A 6.4 A.C. Timing Characteristics 6.4.1 PCI CLOCK Symbol Description Tcyc CYCLE TIME Thigh PCI_CLK HIGH TIME Tlow PCI_CLK LOW TIME Tr/Tf PCI_CLK SLEW RATE 6.4.2 PCI Timings PCI_CLK Tval (max) OUTPUT Ton INPUT Symbol Description Tval CLK TO SIGNAL VALID DELAY Ton FLOAT TO ACTIVE DELAY Toff ...
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... AX88140A 6.4.4 MII/SYM Timing MTCLK/SYMTCLK MTXD<3:0>/SYMTXD<3:0> MTXEN/SYMTXEN MRCLK/SYMRCLK MRXD<3:0>/SYMRXD<3:0> MTXEN/SYMTXEN MRXERR,SD Symbol Description Ttclk Cycle time(100Mbps) Ttclk Cycle time(10Mbps) Ttch high time(100Mbps) Ttch high time(10Mbps) Trch low time(100Mbps) Trch low time(10Mbps) Ttv Clock to data valid Tth Data output hold time ...
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... AX88140A 6.4.5 10Mbps serial timing SRL_TCLK SRL_TXD SRL_TXEN SRL_RCLK SRL_RXD SRL_RXEN Symbol Description Tstc SRL_TCLK Cycle time Tstch Clock high time Tstcl Clock low time Tsto Data output delay Tsto1 SRL_TXEN data output delay Tsth Data output hold time Tsrc SRL_RCLK Cycle time ...
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... AX88140A 6.4.6 Boot ROM Read Cycles Boot ROM Byte Read Cycle br_ad<7:0> address 9-2 br_a1 br_a0 brce# Boot ROM Dword Read Cycle br_ad<7:0> address 9-2 br_a1 br_a0 brce# address 17-10 data address 1 address 0 address 17-10 data3 39 ASIX ELECTRONICS CORPORATION PRELIMINARY data2 data1 data0 ...
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... AX88140A 7.0 Package Information pin 1 b AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA ...
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... AX88140A APPENDIX A.1 Boot ROM read cycle ASIX 88140 Boot ROM Byte Read Cycle br_ad<7:0> address 9-2 br_a1 br_a0 brce# 74LS374 ...
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... AX88140A A.2 Power Supply AX88140A power supply is +5V DC DEC 21140 power supply is +3.3V DC A.3 Boundary Scan Test Pins AX88140A do not support boundary scan test pins DEC 21140 supports boundary scan test pins PRELIMINARY 42 ASIX ELECTRONICS CORPORATION ...
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... Volt CMOS process. PCI Interface Schematic: PCI BUS CONNECTOR PCI SLOT The pull high resisters are required for pin REQ#, GNT#, PERR#, and SERR# on MAC for more detail please to check the schematic. B Function Application AX88140A PCI I/O PINS AD[31:0] C/BE[3:0] PAR FRAME# TRDY# IRDY# STOP# ...
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... B.3 Application for Serial ROM Interface AX88140A Serial ROM Interface address 17-10 data address 1 address 74LS374 ...
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... AX88140A B.4 Application for PHY Interface B.4.1 AX88140A, QSI6611, & MTD213 Application Fig - 7 Application for PCS / Serial Mode B.4.2 Application for MII Mode : LEVEL ONE LXT970 MII STA Fig - 8 Application for MII Mode with LXT970 MTD213 10 BASE T Transceiver 10BASE-T Transceiver MII LXT970 PHY Scrambler / A ...
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... AX88140A B.4.3 Application for MII Mode : MYSON MTD972 + MTD971 MII STA Fig - 9 Application for MII Mode with MTD972 +MTD971 B.4.4 Application for MII Mode : DAVICOM DM9101 MII STA Fig - 10 Application for MII Mode with DM9101 10BASE-T Transceiver MII MTD972 PHY + MTD971 T/R Scrambler / A.N. 4B/5B Descrambler ...