ch7009a ETC-unknow, ch7009a Datasheet - Page 35

• Manufacturer Part Number: ch7009a
• Description: Chrontel Ch7009 Dvi / Tv Output Device
• Manufacturer: ETC-unknow

CHRONTEL
Input Clock Register
Bits 3-0 of register IC controls the delay applied to the XCLK signal before latching input data.
GPIO Control Register
Bit 0 of register GPIO controls the polarity of the P-OUT signal. A value of ‘0’ does not invert the clock at the
output pad.
Bit 1 of register GPIO enables the P-OUT signal. A value of ‘1’ drives the P-OUT clock signal out of the
P-OUT / TLDET* pin. A value of ‘0’ disables the P-OUT signal.
Bit 2 of register GPIO enables the hot plug interrupt detection signal to be output from the P-OUT pin. A value of
‘1’ allows the hot plug detect circuit to pull the P-OUT / TLDET* pin low when a change of state has taken place on
the hot plug detect pin. A value of ‘0’ disables the interrupt signal. The two control bits HPIE and POUTE should
not be enabled (set to ‘1’) at the same time.
Bit 3 of register GPIO resets the hot plug detection circuitry. A value of ‘1’ causes the CH7009 to release the
P-OUT / TLDET* pin. When a hot plug interrupt is asserted by the CH7009 (P-OUT / TLDET) the CH7009 driver
should read register 20h to determine the state of the DVI termination. After having read this register, the HPIR bit
should be set high to reset the circuitry, and then set low again.
Bits 5-4 of register GPIO control the GPIO pins. When the corresponding GOENB bits are low, these register
values are driven out of the corresponding GPIO pins. When the corresponding GOENB bits are high, these register
values can be read to determine the level forced into the corresponding GPIO pins.
Bits 7-6 of register GPIO control the direction of the GPIO pins. A value of ‘1’ sets the corresponding GPIO pin to
an input, and a value of ‘0’ sets the corresponding pin to an output.
201-0000-035 Rev 1.1, 5/8/2000
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
BIT:
BIT:
GOENB1 GOENB0 GPIOL1 GPIOL0
Reserved Reserved Reserved Reserved XCMD3 XCMD2 XCMD1
R/W
R/W
7
1
7
1
R/W
R/W
6
1
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
HPIR
R/W
R/W
3
0
3
1
HPIE
R/W
R/W
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
2
0
2
0
POUTE
R/W
R/W
CH7009A
1
0
1
0
IC
1Dh
8
GPIO
1Eh
8
XCMD0
POUTP
R/W
R/W
35
0
0
0
0