UPD44321181GF-A75 NEC [NEC], UPD44321181GF-A75 Datasheet

UPD44321181GF-A75

Manufacturer Part Number

UPD44321181GF-A75

Description

32M-BIT ZEROSB SRAM FLOW THROUGH OPERATION

Manufacturer

NEC [NEC]

Datasheet

1.UPD44321181GF-A75.pdf (24 pages)

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Document No. M15958EJ5V0DS00 (5th edition)

Date Published April 2005 NS CP(K)

Printed in Japan

Description

static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and

output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input

(CLK).

speed, low voltage, high density and wide bit configuration, such as buffer memory.

(“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes

normal operation.

for high density and low capacitive loading.

Features

• Low voltage core supply: V

• Synchronous operation

• 100 percent bus utilization

• Internally self-timed write control

• Burst read / write : Interleaved burst and linear burst sequence

• Fully registered inputs and outputs for flow through operation

• All registers triggered off positive clock edge

• 3.3V or 2.5V LVTTL Compatible : All inputs and outputs

• Fast clock access time : 7.5 ns (117 MHz)

• Asynchronous output enable : /G

• Burst sequence selectable : MODE

• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

• Separate byte write enable : /BW1 to /BW4 (

• Three chip enables for easy depth expansion

• Common I/O using three state outputs

The

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State

The

PD44321181 and

PD44321181 is a 2,097,152-word by 18-bit and the

PD44321181 and

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with NEC Electronics sales

representative for availability and additional information.

PD44321361 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness

PD44321361 are optimized to eliminate dead cycles for read to write, or write to read

PD44321361 are suitable for applications which require synchronous operation, high

FLOW THROUGH OPERATION

/BW1 and /BW2 (

= 3.3 ± 0.165 V / 2.5 ± 0.125 V

32M-BIT ZEROSB

The mark

PD44321361)

PD44321181)

DATA SHEET

shows major revised points.

µ PD44321181, 44321361

PD44321361 is a 1,048,576-word by 36-bit ZEROSB

MOS INTEGRATED CIRCUIT

SRAM

2002, 2005

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