DS26303G-120 MAXIM [Maxim Integrated Products], DS26303G-120 Datasheet - Page 53

• Manufacturer Part Number: DS26303G-120
• Description: 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
• Manufacturer: MAXIM [Maxim Integrated Products]

6 FUNCTIONAL DESCRIPTION
6.1 Power-Up and Reset
Internal Power_On_Reset circuitry generates a reset during power-up. All registers are reset to the default values.
Writing to the software-reset register generates at least 1ms reset cycle, which has the same effect as the power-up
reset. A reset can also be performed in software by writing to
6.2 Master Clock
The DS26303 requires 2.048MHz ±50ppm or 1.544MHz ±50ppm or multiple thereof. The receiver uses the MCLK
as a reference for clock recovery, jitter attenuation, and generating RCLK during LOS. The AIS transmission uses
MCLK for transmit all-ones condition. See register
MCLK is whatever the incoming frequency is.
MCLK or RCLK can also be used to output CLKA. Register
and the TECLK. Any RCLK can also be selected as an input to the clock generator using this same register. For a
detailed description of selections available, see
Figure 6-1. Pre-Scaler PLL and Clock Generator
MCLK
MPS1..0
Scaler
PLL
Pre
FREQS
RLCK1..8
PLLE
PLLE
E1CLK
T1CLK
Figure
MC
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
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6-1.
to set desired incoming frequency. If the PLLE bit is not set,
PCLKS2..0
SWR
CCR
register.
is used to select the clock generated for CLKA
PCLKI1..0
TECLKS
CLKA3..0
GEN
CLK
TECLKI
RLOS1
RLOS16
CLKAI
TECLKE
CLKAE
TECLK
CLKA