UPD75206CW NEC [NEC], UPD75206CW Datasheet - Page 12

• Manufacturer Part Number: UPD75206CW
• Description: 4-BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC [NEC]

12
0 0 0 A H
0 0 0 C H
A d d r e s s
0 0 0 E H
4.
0 0 0 0 H
0 0 0 2 H
0 0 0 4 H
0 0 0 6 H
0 0 0 8 H
0 0 2 0 H
0 0 7 F H
0 0 8 0 H
0 7 F F H
0 8 0 0 H
0 F F F H
1 0 0 0 H
Remarks
1 7 7 F H
The PD75206 has the following three architectural features.
Figures 4-1, 4-2 shows memory maps of PD75206.
PD75206 ARCHITECTURE AND MEMORY MAP
MBE
MBE
MBE
MBE
MBE
MBE
MBE
MBE
Data memory bank configuration:
General register bank configuration: 8 x 4 banks (Operated in 4 bits)
Memory mapped I/O
In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC
changed is enabled by BR PCDE and BR PCXA instructions.
7
RBE
RBE
RBE
RBE
RBE
RBE
RBE
RBE
6
5
0
0
0
0
0
0
0
0
GETI Instruction Reference Table
Internal Reset Start Address (Most Significant 5 Bits)
Internal Reset Start Address (Least Significant 8 Bits)
INTBT/INT4 Start Address
INTBT/INT4 Start Address
INT0 Start Address
INT0 Start Address
INT1 Start Address
INT1 Start Address
INTSIO Start Address
INTSIO Start Address
INTT0 Start Address
INTT0 Start Address
INTTPG Start Address
INTTPG Start Address
INTKS Start Address
INTKS Start Address
Fig. 4-1 Program Memory Map
Static RAM (320 words x 4 bits)
Display data memory (49 words x 4 bits)
Peripheral hardware (128 x 4 bits)
4 x 4 banks (Operated in 8 bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
(Most Significant 5 Bits)
(Least Significant 8 Bits)
0
CALLF
!faddr
Instruction
Entry Address
BRCB
!caddr
Instruction
Branch Address
BR $addr Instruction
Relative Branch
Address
(-15 to -1 and +2 to +16)
CALL !addr
Instruction
Subroutine Entry
Address
BR !addr
Instruction
Branch Address
Branch Destination
Address and
Subroutine Entry
Address to be Set
by GETI Instruction
PD75206