DS1963L-F5 DALLAS [Dallas Semiconductor], DS1963L-F5 Datasheet
DS1963L-F5
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DS1963L-F5 Summary of contents
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... Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, approved under Entity Concept for use in Class I, Division 1, Group and D Locations (application pending) F5 MICROCAN 5.89 0.36 DATA GROUND All dimensions in millimeters. ORDERING INFORMATION DS1963L-F5 EXAMPLES OF ACCESSORIES DS9096P TM DS9101 DS9093RA DS9093F DS9092 DS1963L TM 0.51 c 1993 16 ...
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... Figure 2. Each of these counters is associated with one of the 256-bit memory pages. The four counters of the DS1963L are associated with pages 12 to 15. The contents of the counter are read together with the memory data using a special command. The bus master must first provide one of the six ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Overdrive-Skip ROM or 6) Overdrive-Match ROM ...
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... LASERED ROM Each DS1963L contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4 ...
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... HIERARCHCAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 1-WIRE BUS BUS MASTER COMMAND LEVEL: 1-WIRE ROM FUNCTION COMMANDS (SEE FIGURE 9) DS1963L SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE 7) 64-BIT LASERED ROM Figure 3 MSB 8-BIT CRC CODE MSB LSB MSB 1-WIRE CRC GENERATOR Figure 4 DS1963L ...
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... TA1, TA2 and E/S. The master may obtain the contents of these registers by reading the scratchpad or derive it from the target address and the amount of data to be written. As soon as the DS1963L has received these bytes correctly, it will copy the data to the requested location beginning at the target address. ...
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... CRC generated by the DS1963L. The memory address range of the DS1963L is 0000H to 01FFH. If the bus master sends a target address higher than this, the internal circuitry of the chip will set the seven most significant address bits they are shifted into the internal address register ...
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... The ending offset/data status byte is unaffected. The hardware of the DS1963L provides a means to accomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers recommended to packetize data into data packets of the size of one memory page each ...
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... The Read Memory + Counter command is used to read memory data together with the write cycle counter associated with the addressed page of data memory. The additional information is transmitted by the DS1963L as the end of a memory page is encountered. Following the current value of the page write cycle counter the DS1963L transmits 32 tamper-detect bits and a 16-bit CRC generated by the DS1963L. ...
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... MEMORY FUNCTION FLOW CHART Figure DS1963L ...
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... MEMORY FUNCTION FLOW CHART Figure 7 cont’ DS1963L ...
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... MEMORY FUNCTION FLOW CHART Figure 7 cont’ DS1963L ...
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... E/S Reset Reset pulse Presence Presence pulse CCh Issue “skip ROM” command F0h Issue “read memory” command 00h TA1, beginning offset=0 00h TA2, address=0000h Read entire memory Reset Reset pulse Presence Presence pulse, done COMMENTS AUTHORIZATION CODE DS1963L ...
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... Read (inverted) CRC16 Reset Reset pulse Presence Presence pulse CCh Issue “skip ROM” command 5Ah Issue “copy scratchpad” command TA1 80h 01h TA2 1Fh E/S Read Copy scratchpad response Reset Reset pulse Presence Presence pulse, done COMMENTS AUTHORIZATION CODE DS1963L ...
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... To facilitate this, each device attached to the 1-Wire bus must have open drain or 3-state outputs. The 1-Wire port of the DS1963L is open drain with an internal circuit equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At regular speed the 1-Wire bus has a maximum data rate of 16 ...
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... This command allows the bus master to read the DS1963L’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS1963L on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result) ...
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... The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive speed, allows the bus master to address a specific DS1963L on a multidrop bus and to simultaneously set it in Overdrive Mode. Only the DS1963L that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command ...
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... ROM FUNCTIONS FLOW CHART Figure DS1963L ...
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... ROM FUNCTIONS FLOW CHART Figure 9 cont’ DS1963L ...
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... DS1963L. During write time slots, the delay circuit determines when the DS1963L will sample the data line. For a read data time slot “0” transmitted, the delay circuit determines how long the DS1963L will hold the data line low overriding the 1 generated by the master. If the data bit is a “ ...
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... MASTER Regular Speed Overdrive Speed 120 SLOT LOW1 REC Regular Speed Overdrive Speed 120 LOW0 SLOT REC DS1963L SLOT LOW1 t REC LOW0 SLOT t REC ...
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... ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS1963L to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial ...
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... CRC–16 HARDWARE DESCRIPTION AND POLYNOMIAL Figure POLYNOMIAL = DS1963L ...
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... PDH t 60 PDL =2.8V to 6.0V; -40°C to +70°C) PUP MAX UNITS V +0.8 V 0 MAX UNITS 800 pF =2.8V to 6.0V; -40°C to +70°C) PUP MAX UNITS 120 120 240 s DS1963L NOTES 1,8 1 25°C) A NOTES 6 NOTES ...
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... PUP may have to be reduced to as much as 0.5V to always ILMAX =2.8V to 6.0V; -40°C to +70°C) PUP MAX UNITS resistor is used to DS1963L NOTES 5 4 ...