UPD77110GC NEC [NEC], UPD77110GC Datasheet
UPD77110GC
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UPD77110GC Summary of contents
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FIXED-POINT DIGITAL SIGNAL PROCESSORS DESCRIPTION The PD77110, 77111, and 77112 are 16-bit fixed-point digital signal processors (DSPs). Compared with the PD77016 family, these DSPs have improved power consumption and are ideal for battery- powered mobile terminals such as PDAs ...
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ORDERING INFORMATION Part Number PD77110GC-9EU PD77111GK-xxx-9EU PD77111F1-xxx-CN1 PD77112GC-xxx-9EU Remark xxx indicates ROM code suffix. 2 Package 100-pin plastic TQFP (fine pitch) (14 14 mm) 80-pin plastic TQFP (fine pitch) (12 12 mm) 80-pin plastic fine-pitch BGA (9 9 mm) 100-pin ...
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External memory Peripheral units X memory Serial data I/O #1 addressing unit Data memory unit Serial I/O #2 Port Interrupt control Host I/O Wait controller Note 1 INT1 - INT4 Notes 1. The WAKEUP pin is multiplexed with the INT4 ...
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PIN CONFIGURATION Serial interface #1 Serial interface #2 Port (4) (2) Host interface (8) For debugging (2) (4) Notes 1. These pins are provided only on the PD77110. 2. With the PD77111 and 77112, the function of this pin can ...
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DSP FUNCTION LIST Item PD77016 Memory space Internal instruction RAM 1.5K 32 (words bits) None Internal instruction ROM Data RAM 2K 16 each (X/Y memory) Data ROM None (X/Y memory) External instruction 48K 32 memory External data memory 48K 16 ...
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PIN CONFIGURATION 100-pin plastic TQFP (fine-pitch) (14 PD77110GC-9EU PD77112GC-xxx-9EU 100 GND 1 Note 1 DA14/NC 2 ...
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Pin No. Pin Name Pin No. 1 GND 26 2 DA14/ DA13 28 4 DA12 29 5 DA11 30 6 DA10 31 7 DA9 32 8 DA8 33 9 DA7 34 10 DA6 35 11 DA5 36 12 ...
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TQFP (fine-pitch) (12 PD77111GK-xxx-9EU GND GND ...
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Pin No. Pin Name Pin No. 1 GND GND 31 ...
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BGA (9 9 mm) PD77111F1-xxx-CN1 (Bottom View Pin No. Pin Name Pin No INT2 C5 Note INT4/WAKEUP ...
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PIN NAME BSTB : Bus Strobe CLKIN : Clock Input CLKOUT : Clock Output D0 - D15 : 16-bit Data Bus DA0 - DA14 : External Data Memory Address Bus EV : Power Supply for I/O Pins DD GND : ...
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PIN FUNCTION ................................................................................................................................. 13 1.1 Pin Function Description .......................................................................................................... 13 1.2 Connection of Unused Pins...................................................................................................... 18 2. FUNCTION OUTLINE........................................................................................................................ 20 2.1 Program Control Unit ................................................................................................................ 20 2.2 Arithmetic Unit ........................................................................................................................... 21 2.3 Data Memory Unit ...................................................................................................................... 22 2.4 Peripheral ...
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PIN FUNCTION Because the pin numbers differ depending on the package, refer to the diagram of the package to be used. 1.1 Pin Function Description • Power supply Pin No. Pin Name 100-pin 80-pin 80-pin TQFP TQFP FBGA IV ...
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Interrupt Pin No. Pin Name 100-pin 80-pin 80-pin TQFP TQFP FBGA INT1 - INT3 D4, A3, B4 INT4 • External data memory interface Pin No. Pin Name 100-pin 80-pin 80-pin ...
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Serial interface Pin No. Pin Name 100-pin 80-pin 80-pin TQFP TQFP FBGA SCK1 SORQ1 SOEN1 SO1 SIEN1 SI1 SIAK1 40 25 ...
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Host interface Pin No. Pin Name 100-pin 80-pin 80-pin TQFP TQFP FBGA HA1 HA0 HCS HRD HWR HRE HWE 67 53 ...
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Debugging interface Pin No. Pin Name 100-pin 80-pin 80-pin TQFP TQFP FBGA TDO TICE TCK TDI TMS TRST • Others Pin ...
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Connection of Unused Pins 1.2.1 Connection of Function Pins When mounting, connect unused pins as follows: Pin I/O INT1 - INT4 Input Connect to EV X/Y Output Leave unconnected. DA0 - DA14 Output Note D15 I/O ...
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Connection of no-function pins Pin I/O I.C. Leave unconnected. NU Connect Leave unconnected. PD77110, 77111, 77112 Recommended Connection . DD Data Sheet U12801EJ4V0DS00 19 ...
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FUNCTION OUTLINE 2.1 Program Control Unit This unit is used to execute instructions, and control branching, loops, interrupts, the clock, and the standby mode of the DSP. 2.1.1 CPU control A three-stage pipeline architecture is employed and almost all ...
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Arithmetic Unit This unit performs multiplication, addition, logical operations, and shift, and consists of a 40-bit multiply accumulator, 40-bit data ALU, 40-bit barrel shifter, and eight 40-bit general-purpose registers. 2.2.1 General-purpose registers (R0 through R7) These eight 40-bit registers ...
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Data Memory Unit The data memory unit consists of two banks of data memory and two data addressing units. 2.3.1 Data memory The capacity and type of the memory differ depending on the model of the DSP. All DSPs ...
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Wait cycle register The number of wait cycles to be inserted when the external data memory area is accessed can be specified in Note advance by using a register (DWTR) . The number of wait cycles that can be ...
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Initializing PLL Initializing the PLL starts from the 1024th input clock after the RESET pin has been asserted active (low level). Initialization takes 1024 clocks and it takes the PLL 100 locked. After that, the DSP ...
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Self boot The boot-up ROM transfers the instruction code stored in the data memory space to the instruction RAM, based on the boot parameter written to address 0x4000 of the Y data memory. Generally, with a mask ROM model ...
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Host reboot An instruction code is obtained via the host interface and transferred to the instruction RAM. With the PD77110, the host reboot mode is used to boot up the instruction RAM from addresses 0x4000 through 0xBFFF. Areas 0x0200 ...
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STOP Mode To set this mode, execute the STOP instruction. In this mode, all the functions, including the clock circuit and PLL, are stopped and the power consumption is minimized with only leakage current flowing. To release the STOP ...
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Interrupt vector table Addresses 0x200 through 0x23F of the instruction memory are entry points (vectors) of interrupts. instruction addresses are assigned to each interrupt source. 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 ...
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Data Memory 7.2.1 Data memory map The data memory space consists memory space and a Y memory space of 64K words the memory capacity and memory type differ depending on the product. PD77110 0xFFFF External data ...
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Internal peripherals The internal peripherals are mapped to the internal data memory space. X/Y Memory Address Register Name 0x3800 SDT1 0x3801 SST1 0x3802 SDT2 0x3803 SST2 0x3804 PDT 0x3805 PCD 0x3806 HDT 0x3807 HST 0x3808 DWTR 0x3809 - 0x383F ...
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When the PLL multiple is m, output division ratio is n, and halt division ratio is l, the relationship between each operation mode and operating clock is as follows: Operation Mode Normal operation mode HALT mode STOP mode The PLL ...
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Settings related to clock control External pins PLL0 through PLL2 are used to set the multiple of the PLL. PLL0 and PLL1 are multiplexed with general-purpose I/O ports P2 and P3, and can be used as PLL setting pins ...
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INSTRUCTIONS 9.1 Outline of Instructions An instruction consists of 32 bits. Almost all the instructions, except some such as branch instructions, are executed with one system clock. The maximum instruction cycle of the instruction cycle of the PD77111 and ...
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Instruction Set and Operation An operation is written in the operation field for each instruction in accordance with the operation representation format of that instruction. If two or more parameters can be written, select one of them. (a) Representation ...
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Modifying data pointer The data pointer is modified after the memory has been accessed. The result of modification becomes valid starting from the instruction that immediately follows. The data pointer cannot be modified. Example DPn Nothing is done (value ...
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Instruction Set Instruc- Instruction Mnemonic tion Name Trinomial Multiply add operation Multiply sub Sign unsign multiply add ( ...
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Instruc- Instruction Mnemonic tion Name Binomial Less than (ro operation Uninom- Clear CLR (ro) inal Increment operation Decrement Absolute value ro = ABS (ro ...
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Instruc- Instruction Mnemonic tion Name Load/ Parallel ro = *dpx_mod ro = Notes 1, 2 store load/store *dpy_mod ro = *dpx_mod *dpy_mod = rh *dpx_mod = *dpy_mod *dpx_mod = rh *dpy_mod = rh Partial load/ dest = ...
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Instruc- Instruction Mnemonic tion Name Branch Jump JMP imm Register JMP dp indirect jump Subroutine call CALL imm Register CALL dp indirect subroutine call Return RET Interrupt return RETI Hard- Repeat REP count ware loop Loop LOOP count (instruction of ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( Parameter Symbol Supply voltage Input voltage V I Output voltage V O Storage temperature T stg Operating temperature T A Caution If any of the ...
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DC Characteristics ( +85 C, with IV A Parameter Symbol High-level input voltage V IHN V IHS Low-level input voltage V IL High-level output voltage V OH Low-level output voltage V OL High-level input leakage I LH ...
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PD77110 (1) PD77110 AC Characteristics (Unless otherwise specified, T recommended operating condition range) Clock Timing requirements Parameter Symbol Note 1 CLKIN cycle time t cCX CLKIN high-level width t wCXH CLKIN low-level width t wCXL CLKIN rise/fall time t rfCX ...
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Switching characteristics Parameter Symbol Note Internal clock cycle t cC CLKOUT cycle time t cCO CLKOUT width t wCO CLKOUT rise/fall time t rfCO CLKOUT delay time t dCO Note m: Multiple, l: HALT division ratio Clock I/O timing t ...
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PD77110 Reset, Interrupt Timing requirements Parameter Symbol RESET low-level width t w (RL) RESET recovery time t rec (R) WAKEUP low-level width t w (WAKEUPL) INT1 - INT4 low-level width t w (INTL) INT1 - INT4 recovery time t rec ...
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External Data Memory Access Timing requirements Parameter Symbol Read data setup time t suDDRD Read data hold time t hDDRD Switching characteristics Parameter Symbol Address cycle time t rcDA Address output hold time t hDA MRD output delay time t ...
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PD77110 External data memory access timing (read) DA0 - DA14 X/Y t MRD D0 - D15 External data memory access timing (write) DA0 - DA14 X/Y t dDW MWR t vDDWD Hi D15 46 t rcDA dDR t ...
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Bus Arbitration Timing requirements Parameter Symbol HOLDRQ setup time t suHRQ HOLDRQ hold time t hHRQ Switching characteristics Parameter Symbol BSTB hold time t hBS BSTB output delay time t dBS HOLDAK output delay time t dHAK Data hold time ...
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PD77110 Bus arbitration timing (when bus is idle) CLKIN (Bus busy) Bus idle t hBS BSTB t suHRQ HOLDRQ HOLDAK X/Y, DA0 - DA14, MRD, MWR Bus arbitration timing (when bus is busy) CLKIN (Bus busy) BSTB t suHRQ HOLDRQ ...
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Serial Interface Timing requirements Parameter Symbol SCK cycle time t cSC SCK high-/low-level width t wSC SCK rise/fall time t rtSC SOEN setup time t suSOE SOEN hold time t hSOE SIEN setup time t suSIE SIEN hold time t ...
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PD77110 Serial output timing 1 t cSC t t wSC wSC SCK1, SCK2 t dSOR SORQ1 t suSOE t hSOE SOEN1, SOEN2 Hi-Z SO1, SO2 Serial output timing 2 (during successive output) t cSC t t wSC wSC SCK1, SCK2 ...
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Serial input timing 1 t cSC t t wSC wSC SCK1, SCK2 t dSIA SIAK1 t suSIE t hSIE SIEN1, SIEN2 SI1, SI2 Serial input timing 2 (during successive input) t cSC t t wSC wSC SCK1, SCK2 t dSIA ...
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PD77110 Host Interface Timing requirements Parameter Symbol HRD delay time t dHR HRD width t wHR HCS, HA0, HA1, read hold t hHCAR time HCS, HA0, HA1 line hold time t hHCAW HRD, HWR recovery time t recHS HWR delay ...
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Host read interface timing CLKIN HCS, HA0, HA1 HRD HD0 - HD7 t dHE HRE Host write interface timing CLKIN HCS, HA0, HA1 HWR HD0 - HD7 t dHE HWE PD77110, 77111, 77112 t hHCAR t dHR t wHR t ...
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PD77110 General-purpose I/O Port Timing requirements Parameter Symbol Port input setup time t suPI Port input hold time t hPI Switching characteristics Parameter Symbol Port output delay time t dPO General-purpose I/O port timing CLKIN (Output) P0 ...
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Debugging Interface (JTAG) Timing requirements Parameter Symbol TCK cycle time t cTCK TCK high-/low-level width t wTCK TCK rise/fall time t rfTCK TMS, TDI setup time t suDI TMS, TDI hold time t hDI Input pin setup time t suJIN ...
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PD77111, 77112 (2) PD77111, 77112 AC Characteristics (T operating condition range) Clock Timing requirements Parameter Symbol Note 1 CLKIN cycle time t cCX CLKIN high-level width t wCXH CLKIN low-level width t wCXL CLKIN rise/fall time t rfCX Internal clock ...
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Clock I/O timing t cCX t wCXH CLKIN Internal clock t dCO t wCO CLKOUT PD77110, 77111, 77112 t t wCXL t t cC, cC(R) t cCO t wCO Data Sheet U12801EJ4V0DS00 PD77111, 77112 t rfCX rfCX t t rfCO ...
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PD77111, 77112 Reset, Interrupt Timing requirements Parameter Symbol RESET low-level width t w (RL) RESET recovery time t rec (R) WAKEUP low-level width t w (WAKEUPL) INT1 - INT4 low-level width t w (INTL) INT1 - INT4 recovery time t ...
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External Data Memory Access ( PD77112 only) Timing requirements Parameter Symbol Read data setup time t suDDRD Read data hold time t hDDRD Switching characteristics Parameter Symbol Address cycle time t rcDA Address output hold time t hDA MRD output ...
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PD77111, 77112 External data memory access timing (read) DA0 - DA13 X/Y t MRD D0 - D15 External data memory access timing (write) DA0 - DA13 X/Y t dDW MWR t vDDWD Hi D15 60 t rcDA dDR ...
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Bus Arbitration ( PD77112 only) Timing requirements Parameter Symbol HOLDRQ setup time t suHRQ HOLDRQ hold time t hHRQ Switching characteristics Parameter Symbol BSTB hold time t hBS BSTB output delay time t dBS HOLDAK output delay time t dHAK ...
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PD77111, 77112 Bus arbitration timing (when bus is idle) CLKIN (Bus busy) Bus idle t hBS BSTB t suHRQ HOLDRQ HOLDAK X/Y, DA0 - DA13, MRD, MWR Bus arbitration timing (when bus is busy) CLKIN (Bus busy) BSTB t suHRQ ...
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Serial Interface Timing requirements Parameter Symbol SCK cycle time t cSC SCK high-/low-level width t wSC SCK rise/fall time t rfSC SOEN setup time t suSOE SOEN hold time t hSOE SIEN setup time t suSIE SIEN hold time t ...
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PD77111, 77112 Caution If noise is superimposed on the serial clock, the serial interface may be deadlocked. Bear in mind the following points when designing your system: • Reinforce the wiring for power supply and ground (if noise is superimposed ...
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Serial output timing 1 t cSC t t wSC wSC SCK1, SCK2 t dSOR SORQ1 t suSOE t hSOE SOEN1, SOEN2 Hi-Z SO1, SO2 Serial output timing 2 (during successive output) t cSC t t wSC wSC SCK1, SCK2 t ...
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PD77111, 77112 Serial input timing 1 t cSC t t wSC wSC SCK1, SCK2 t dSIA SIAK1 t suSIE t hSIE SIEN1, SIEN2 SI1, SI2 Serial input timing 2 (during successive input) t cSC t t wSC wSC SCK1, SCK2 ...
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Host Interface Timing requirements Parameter Symbol HRD delay time t dHR HRD width t wHR HCS, HA0, HA1, read hold t hHCAR time HCS, HA0, HA1 line hold time t hHCAW HRD, HWR recovery time t recHS HWR delay time ...
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PD77111, 77112 Host read interface timing CLKIN HCS, HA0, HA1 HRD HD0 - HD7 t dHE HRE Host write interface timing CLKIN HCS, HA0, HA1 HWR HD0 - HD7 t dHE HWE 68 PD77110, 77111, 77112 t hHCAR t dHR ...
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General-purpose I/O Port Timing requirements Parameter Symbol Port input setup time t suPI Port input hold time t hPI Switching characteristics Parameter Symbol Port output delay time t dPO General-purpose I/O port timing CLKIN (Output ...
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Debugging Interface (JTAG) Timing requirements Parameter Symbol TCK cycle time t cTCK TCK high-/low-level width t wTCK TCK rise/fall time t rfTCK TMS, TDI setup time t suDI TMS, TDI hold time t hDI Input pin setup time t suJIN ...
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Debugging interface timing t cTCK t t wTCK wTCK TCK t suTRST TRST TMS, TDI TDO Capture state Update state Remark For details of JTAG, refer to IEEE1149.1. PD77110, 77111, 77112 t rfTCK t suDI t hDI Valid Valid Valid ...
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PACKAGE 100-PIN PLASTIC TQFP (FINE PITCH) (14x14 100 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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PLASTIC TQFP (FINE PITCH) (12x12 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. PD77110, 77111, 77112 ...
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PLASTIC FBGA (9x9 Index mark Data Sheet ...
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RECOMMENDED SOLDERING CONDITIONS It is recommended to solder this product under the following conditions. For details of the recommended soldering conditions, refer to information document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). For soldering methods and conditions other than those ...
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PD77111F1-xxx-CN1: 80-pin plastic fine-pitch BGA (9 Process Infrared ray reflow Package peak temperature: 230 C, Time: 30 seconds MAX (210 C MIN), Number of times: 2 MAX, Number of days: 3 necessary for 10 hours) VPS Package peak temperature: 215 ...
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PD77110, 77111, 77112 Data Sheet U12801EJ4V0DS00 77 ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They ...
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The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a ...