ssd1800 ETC-unknow, ssd1800 Datasheet - Page 15

• Manufacturer Part Number: ssd1800
• Description: 80x16 + 1 Icon Line Lcd Segment / Common Driver With Controller For Character Display System
• Manufacturer: ETC-unknow

8
8.1 Command Decoder and Command Interface
based upon the input of the D/ C pin. If D/ C is high, data is written to internal memories (DDRAM, CGRAM,
ICONRAM). If D/ C is low, the input at D
the corresponding command register.
8.2 MPU Parallel 6800-series Interface in 8 bits bus mode
input high indicates a read operation from the internal RAM (DDRAM, CGRAM and ICONRAM). R/W ( WR ) input low
indicates a write operation to internal RAM (DDRAM, CGRAM and ICONRAM) or Internal Command Registers
depending on the status of D/ C input. The E( RD ) input serves as data latch signal (clock) when high provided that
processings are internally performed which require the insertion of a dummy read before the first actual display data
read. This is shown in Figure 4 below. The dummy read make the address counter (AC) increased by 1. So it is
recommended to set address again before writing. The consecutive read after the dummy read are also the valid
data. The instruction read cycle is not supported and it is regarded as a no operation cycle.
8.3 MPU Parallel 8080-series Interface in 8 bits bus mode
serves as data read latch signal (clock) when low provided that CS is low whether it is Command write or internal
RAM read/ write is controlled by D/ C . R/W ( WR ) input serves as data write latch signal (clock) when low provided
that CS is low. Refer to Figure 21 for Parallel Interface Timing Diagram of 8080-series microprocessor.
8.4 4-bit MPU Parallel 6800/8080-Series Interface
needed to read/ write 8 bits data. For write operation, upper order bits are written before the low order bits, and low
order bits are always read before the upper order bit in read transaction.
8.5 MPU Serial Interface
shift register on every rising edge of SCK in the order of D
determine whether the data byte in the shift register is written to the internal RAM (DDRAM, CGRAM, ICONRAM) or
command register at the same clock.
8.6 Oscillator Circuit
voltage converter. This clock is also used in the Display Timing Generator.
CS are low. Refer to Figure 20 for Parallel Interface Timing Diagram of 6800-series microprocessors.
SSD1800 Series
This module determines whether the input data is interpreted as data or command. Data is directed to this module
The parallel interface consists of 8 bi-directional data pins (D
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
The parallel interface consists of 8 bi-directional data pins (D
Similar to 6800-series interface, a dummy read is also required before the first actual display data read.
The control of 4-bit bus mode is exactly the same as 8-bit bus mode except 2 consecutive access (read/ write) is
The serial interface consists of serial clock SCK (D
This module is an On-Chip low power RC oscillator circuitry. The oscillator generates the clock for the DC-DC
FUNCTIONAL BLOCK DESCRIPTIONS
Rev 1.0
P 15/42 Mar 2004
7
-D
0
is interpreted as a Command and it will be decoded and be written to
6
), serial data SDA (D
7
, D
6
7
7
, ... D
-D
-D
0
0
), R/W ( WR ), D/ C , E( RD ), CS . E( RD ) input
), R/W ( WR ), D/ C , E( RD ), CS . R/W ( WR )
0
. D/ C is sampled on every eighth clock to
7
), D/ C , CS . SDA is shifted into a 8-bit
Solomon Systech