ssd1961 displaytech, ssd1961 Datasheet
ssd1961
Available stocks
Related parts for ssd1961
ssd1961 Summary of contents
Page 1
... Embedded Display SRAM This document contains information on a product under development. Solomon Systech reserves the right to change or discontinue this product without notice. http://www.solomon-systech.com SSD1961 Rev 0.10 P 1/27 SSD1961 Product Preview LCD Display Controller Copyright © 2008 Solomon Systech Limited Mar 2008 ...
Page 2
... Display Format ...........................................................................................................................................14 7.4.2 General Purpose Input/Output (GPIO) ......................................................................................................14 8 COMMAND TABLE ................................................................................................................. 15 9 MAXIMUM RATINGS ............................................................................................................. CHARACTERISTICS..................................................................................................... CHARACTERISTICS..................................................................................................... 19 11.1 MCU I T NTERFACE IMING 11.1.1 6800 Mode ..................................................................................................................................................19 11.1.2 8080 Mode Write Cycle ..............................................................................................................................22 11.2 LCD I T NTERFACE IMING 12 PACKAGE INFORMATION................................................................................................ 25 Solomon Systech M ...............................................................................................................13 ANAGER ....................................................................................................................................19 .....................................................................................................................................24 Mar 2008 P 2/27 Rev 0.10 SSD1961 ...
Page 3
... B S ABLE RAME UFFER ETTINGS T 9- ABLE AXIMUM ATINGS T 10 ABLE HARACTERISTICS T 11-2: 6800 M T ABLE ODE IMING T 11-3: 8080 M T ABLE ODE IMING SSD1961 Rev 0.10 P 3/27 ................................................................................................................. 5 T .................................................................................................... 8 ABLE M ....................................................................................................... 9 IN APPING M ........................................................................................................ 9 APPING M .................................................................................................... 10 IN APPING ...................................................................................................................... 10 ..................................................................................................................... EGRADING TO SET ADDRESS ( OLTAGE EFERENCED TO ...
Page 4
... FIGURES F 4-1: SSD1961 B D IGURE LOCK F 5- IGURE INOUT IAGRAM F 7-1: R IGURE ELATIONSHIP BETWEEN F 7- IGURE TATE IAGRAM OF F 11-1: 6800 M T IGURE ODE IMING F 11-2: 6800 M T IGURE ODE IMING F 11-3: 8080 M T IGURE ODE IMING F 11-4: G TFT P IGURE ENERIC ANEL Solomon Systech ............................................................................................................ 6 IAGRAM – ...
Page 5
... GENERAL DESCRIPTION SSD1961 is a display controller of 5,529,600 bit frame buffer to support up to 640 x 480 x 18bit graphics content. It also equips parallel MCU interfaces in different bus width to receive graphics data and command from MCU. Its display interface supports common RAM-less LCD driver of color depth bit-per- pixel ...
Page 6
... BLOCK DIAGRAM Solomon Systech Figure 4-1: SSD1961 Block Diagram Mar 2008 P 6/27 Rev 0.10 SSD1961 ...
Page 7
... PIN ARRANGEMENT 5.1 64 Pin TFBGA Figure 5-1: Pinout Diagram – 64 pin TFBGA (Top view) . SSD1961 Rev 0.10 P 7/27 Mar 2008 Solomon Systech ...
Page 8
... LDATA13 E1 LDATA12 E2 LDATA11 E3 LDATA10 E4 LDEN E5 LFRAME E6 GPIO1 E7 XTAL_IN E8 LDATA9 F1 LDATA8 F2 LDATA7 F3 LDATA6 F4 VSSIO F5 VDDD F6 D[4] F7 LDATA17 F8 Signal Name Pin # Signal Name LDATA5 G1 D[16] LDATA4 G2 D[14] LDATA3 G3 D[12] LDATA2 G4 D[9] VSSD G5 D[6] R/W#(WR#) G6 D/C# D[3] G7 RESET# CLK G8 D[0] LDATA1 H1 D[17] LDATA0 H2 D[15] D[13] H3 D[11] D[10] H4 D[8] D[7] H5 D[5] E(RD#) H6 D[2] H7 CONF D[1] H8 VDDIO Mar 2008 P 8/27 Rev 0.10 SSD1961 CS# ...
Page 9
... Type Pin # LFRAME O LLINE O LSHIFT O LDEN O LDATA[17:0] O GPIO[3:0] IO GAMAS [1:0] O PWM O SSD1961 Rev 0.10 P 9/27 Table 6-1: MCU Interface Pin Mapping Description E8 TTL clock input C8 Crystal oscillator input Crystal oscillator output B8 Chip select H6 G6 Data/Command select 6800 mode: E (enable signal) F6 8080 mode: RD# (read strobe signal) ...
Page 10
... Power supply for LCD interface related pads A1 Power supply for internal analog circuit and analog A8 I/O pads Power supply for digital I/O pads H8 E5 Ground for internal digital circuit A7 Ground for internal analog circuit and analog I/O pads Ground for digital I/O pads D5 Mar 2008 P 10/27 Rev 0.10 SSD1961 ...
Page 11
... MCU Interface The MCU interface connects the MCU and SSD1961 graphics controller. The MCU interface can be configured as 6800 mode and 8080 mode by the CONF pin. By pulling the CONF pin to VSSIO, the MCU interface will be configured as 6800 mode interface. If the CONF pin is connected to VDDIO, the MCU interface will be configure in 8080 mode ...
Page 12
... Frame Buffer There are 5,529,600 bit built-in SRAM inside SSD1961 to use as frame buffer. When the frame buffer is written or read, the “address counter” will automatically increase by one or decrease by one depends on the frame buffer settings. Solomon Systech Mar 2008 P 12/27 Rev 0 ...
Page 13
... The System Clock and Reset Manager also manage the reset signals to ensure all the module are reset to appropriate status when the system are in reset state, deep sleep state, sleep state and display state. Figure 7-2 shows a state diagram of four operation states of SSD1961. SSD1961 Rev 0 ...
Page 14
... LCD Controller 7.4.1 Display Format The LCD controller reads the frame buffer and generates display signals according to the selected display panel format. SSD1961 supports common RAM-less TFT driver using generic RGB data format or TTL format. 7.4.2 General Purpose Input/Output (GPIO) The GPIO pins can operate in 2 modes, GPIO mode and miscellaneous display signal mode. When the pins are configured as GPIOs, these pins can be controlled directly by MCU ...
Page 15
... SSD1961 Rev 0.10 P 15/27 No operation Software Reset Get the current power mode Get the frame memory to the display panel read order Get the current pixel format The display module returns the Display Signal Mode. ...
Page 16
... ROP3 operation. No effect if the GPIO1 is configured as general GPIO. Get the GPIO1 properties with respect to the LCD signal generators. Set the GPIO2 with respect to the LCD signal generators using ROP3 operation. No effect if the GPIO2 is configured as general GPIO. Mar 2008 P 16/27 Rev 0.10 SSD1961 ...
Page 17
... E9 Reserved 0x F0 set_pixel_data_interface 0x F1 get_pixel_data_interface 0x FF Reserved SSD1961 Rev 0.10 P 17/27 Get the GPIO2 properties with respect to the LCD signal generators. Set the GPIO3 with respect to the LCD signal generators using ROP3 operation. No effect if the GPIO3 is configured as general GPIO. Get the GPIO3 properties with respect to the LCD signal generators ...
Page 18
... Table 10 Characteristics Test Condition ) SS Unit < < OUT DDIO Unused outputs SS DDIO Min Typ Max TBD TBD TBD TBD TBD TBD TBD TBD TBD Mar 2008 P 18/27 Rev 0.10 SSD1961 . Reliability Unit ...
Page 19
... FDRD t Address Setup Time AS t Address Hold Time AH t Data Setup Time DSW t Data Hold Time DHW t Data Access Time DSR t Output Hold time DHR SSD1961 Rev 0.10 P 19/27 SS Table 11-1: 6800 Mode Timing Mar 2008 Min Typ Max Unit CYC ...
Page 20
... Figure 11-1: 6800 Mode Timing Diagram (Use CS# as Clock) Solomon Systech Mar 2008 P 20/27 Rev 0.10 SSD1961 ...
Page 21
... Figure 11-2: 6800 Mode Timing Diagram (Use E as Clock) SSD1961 Rev 0.10 P 21/27 Mar 2008 Solomon Systech ...
Page 22
... Data Setup Time DSW t Data Hold Time DHW t Data Access Time DSR t Output Hold time DHR Solomon Systech Table 11-2: 8080 Mode Timing Mar 2008 P 22/27 Min Typ Max Unit CYC CYC CYC Rev 0.10 SSD1961 ...
Page 23
... SSD1961 Rev 0.10 P 23/27 Figure 11-3: 8080 Mode Timing Diagram Mar 2008 Solomon Systech ...
Page 24
... LCD Interface Timing VPS LFRAME LLINE LDEN LDATA[17:0] HPS LLINE LSHIFT LDEN HDPS LDATA[17:0] Solomon Systech Figure 11-4: Generic TFT Panel Timing Frame) VPW VDPS Line) HPW HDP VDP Mar 2008 P 24/27 Rev 0.10 SSD1961 ...
Page 25
... PACKAGE INFORMATION SSD1961 Rev 0.10 P 25/27 Mar 2008 Solomon Systech ...
Page 26
... Symbol Solomon Systech Dimension in mm Min Typical -- --- 0.16 --- --- 0.26 --- 0.54 0.27 --- --- 6.00 BSC --- 6.00 BSC --- 0.65 --- 4.55 BSC --- 4.55 BSC Mar 2008 P 26/27 Max 1.1 0.26 --- --- 0.37 --- --- --- --- --- Rev 0.10 SSD1961 ...
Page 27
... Hazardous Substance (RoHS) Directive (2002/95/EC)” and China standard “电子信息产品污染控制标识要求 (SJ/T11364-2006)” with control Marking Symbol . Hazardous Substances test report is available upon requested. http://www.solomon-systech.com SSD1961 Rev 0.10 P 27/27 Mar 2008 ...