A25L40PT-F AMICC [AMIC Technology], A25L40PT-F Datasheet
A25L40PT-F
Related parts for A25L40PT-F
A25L40PT-F Summary of contents
Page 1
Preliminary Document Title 4 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface Revision History Rev. No. History 0.0 Initial issue 0.1 Add the Fast Read Dual Operation Instruction Add QFN 6mm) package type 0.2 ...
Page 2
Preliminary FEATURES 4 Mbit of Flash Memory Flexible Sector Architecture (4/4/8/16/32)KB/64x7 KB Bulk Erase (4 Mbit (typical) Sector Erase (512 Kbit (typical) Page Program (up to 256 Bytes) in 3ms (typical) 2.7 to 3.6V Single Supply ...
Page 3
Block Diagram HOLD W Control Logic Address register and Counter Pin Descriptions Pin No. Description C Serial Clock D Serial Data Input Q Serial Data Output Chip Select S Write Protect W Hold HOLD V Supply ...
Page 4
SIGNAL DESCRIPTION Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used ...
Page 5
Figure 1. Bus Master and Memory Devices on the SPI Bus SDO SPI Interface with SDI (CPOL, CPHA) SCK = ( (1, 1) Bus Master (ST6, ST7, ST9, ST10, Other) CS3 CS2 CS1 Note: The Write Protect ( ...
Page 6
OPERATING FEATURES Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program ...
Page 7
... Table 1. Protected Area Sizes A25L40PT Top Boot Block Status Register Content BP2 Bit BP1 Bit BP0 Bit Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0. 2. The sector 7 include sector 7-0, sector 7-1, sector 7-2, sector 7-3 and sector 7-4. ...
Page 8
Hold Condition The Hold ( HOLD ) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that ...
Page 9
... MEMORY ORGANIZATION The memory is organized as: 524,288 bytes (8 bits each) 8 sectors (one (4/4/8/16/32) Kbytes & 64x7 Kbytes 2048 pages (256 bytes each). Table 2. Memory Organization A25L40PT Top Boot Block Address Table Sector 7-4 7-3 7-2 7-1 7 A25L40PU Bottom Boot Block Address Table Sector ...
Page 10
INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select ( S one-byte instruction ...
Page 11
Write Enable (WREN) The Write Enable (WREN) instruction (Figure 4.) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write ...
Page 12
Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When ...
Page 13
Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) ...
Page 14
Table 5. Protection Modes SRWD W Mode Bit Signal 1 0 Status Register is Writable (if the Software WREN instruction has set the Protected WEL bit) The values in the 0 0 SRWD, BP2, BP1 and BP0 bits (SPM) can ...
Page 15
Read Data Bytes (READ) The device is first selected by driving Chip Select ( The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of ...
Page 16
Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select ( The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy ...
Page 17
Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write ...
Page 18
Sector Erase (SE) The Sector Erase (SE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device ...
Page 19
Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device ...
Page 20
Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device ...
Page 21
Read Device Identification (RDID) The Read Identification (RDID) instruction allows the 8-bit manufacturer identification code to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 37h, plus the continuation ...
Page 22
Release from Deep Power-down Electronic Signature (RES) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Electronic instruction. Executing this instruction takes the device out of the Deep ...
Page 23
Figure 18. Release from Deep Power-down (RES) Instruction Sequence High Impedance Q S Driving Chip Select ( ) High after the 8-bit instruction byte has been received by the device, but before the whole of ...
Page 24
POWER-UP AND POWER-DOWN At Power-up and Power-down, the device must not be S selected (that is Chip Select ( ) must follow the voltage applied until V reaches the correct value (min) at Power-up, ...
Page 25
Table 7. Power-Up Timing Symbol V V (minimum) CC(min (min) to device operation PU CC Note: These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set ...
Page 26
Absolute Maximum Ratings* Storage Temperature (TSTG -65° 150°C Lead Temperature during Soldering (Note 1) D.C. Voltage on Any Pin to Ground Potential . . . . . . ...
Page 27
Table 10. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Standby Current CC1 I Deep Power-down Current CC2 I Operating Current (READ) CC3 I Operating Current (PP) CC4 I Operating Current (WRSR) CC5 ...
Page 28
Figure 20. AC Measurement I/O Waveform 0.8V 0.2V PRELIMINARY (May, 2007, Version 0.4) Input Levels A25L40P Series Input and Output Timing Reference Levels 0.7V CC 0.5V CC 0.3V CC AMIC Technology Corp. ...
Page 29
Table 13. AC Characteristics Alt. Symbol f f Clock Frequency for the following instructions: FAST_READ PP, SE, BE, DP, RES, RDID, WREN, WRDI, RDSR, WRSR f Clock Frequency for READ instructions Clock High Time ...
Page 30
Figure 21. Serial Input Timing S tCHSL C tDVCH D Q Figure 22. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL PRELIMINARY (May, 2007, Version 0.4) tSLCH tCHDX MSB IN High Impedance ...
Page 31
Hold Timing Figure 23 HOLD Figure 24. Output Timing ADDR.LSB IN tCLQV tCLQX tCLQX Q PRELIMINARY (May, 2007, Version 0.4) tHLCH tCHHL tCHHH tHLQZ tCH tCLQV 30 A25L40P Series tHHCH tHHQX tCL tSHQZ ...
Page 32
Part Numbering Scheme * Optional PRELIMINARY (May, 2007, Version 0.4) Package Material Blank: normal F: PB free Temperature* Package M = 209 mil SOP SOP 150 mil SOP QFN 8 Boot ...
Page 33
... Ordering Information Part No. Speed (MHz) (2.7V~3.6V)/ (3.0V~3.6V) A25L40PT-F A25L40PT-UF A25L40PTO-F A25L40PTO-UF A25L40PTM-F 75/85 A25L40PTM-UF A25L40PTN-F A25L40PTN-UF A25L40PTQ-F A25L40PTQ-UF A25L40PU-F A25L40PU-UF A25L40PUO-F A25L40PUO-UF A25L40PUM-F 75/85 A25L40PUM-UF A25L40PUN-F A25L40PUN-UF A25L40PUQ-F A25L40PUQ- for industrial operating temperature range: -40°C ~ +85°C PRELIMINARY (May, 2007, Version 0.4) Active Read Program/Erase Current Current Typ ...
Page 34
Package Information P-DIP 8L Outline Dimensions Symbol Notes: 1. Dimension D and E 2. Dimension B 3. Tolerance: ±0.010” (0.25mm) unless otherwise specified. PRELIMINARY (May, 2007, Version 0.4) Dimensions in inches Min Nom Max 0.180 A 0.015 ...
Page 35
Package Information SOP 8L (150mil) Outline Dimensions e D PRELIMINARY (May, 2007, Version 0.4) b ° 8 ° Symbol Dimensions 1.35~1.75 A 0.10~0. 0.33~0.51 D 4.7~5.0 E 3.80~4.00 e 1.27 BSC H 5.80~6.20 ...
Page 36
Package Information SOP 8L (209mil) Outline Dimensions PRELIMINARY (May, 2007, Version 0. GAGE PLANE SEATING PLANE b Dimensions in mm Symbol Min Nom A 1.75 1.95 A 0.05 0. 1.70 1.80 2 ...
Page 37
Package Information SOP 16L (300mil) Outline Dimensions 16 1 0.016 typ. PRELIMINARY (May, 2007, Version 0. 0.050 typ. SEATING PLANE 0.004max. Dimensions in inch Symbol Min A 0.093 A 0.004 1 D 0.398 E 0.291 H 0.394 ...
Page 38
Package Information QFN 0.8mm) Outline Dimensions 4 5 Seating Plane PRELIMINARY (May, 2007, Version 0.4) 1 0.25 C Pin1 ID Area 0. Dimensions in mm Symbol Min Nom Max ...