PLL520-20 PhaseLink (PLL), PLL520-20 Datasheet

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PLL520-20

Manufacturer Part Number
PLL520-20
Description
, 120-200MHz In, 120-200MHz Out, Pecl,lvds
Manufacturer
PhaseLink (PLL)
Datasheet
FEATURES
DESCRIPTIONS
PLL520-20 is a VCXO IC specifically designed to
pull high frequency fundamental crystals. Its design
was optimized to tolerate higher limits of
interelectrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. Its internal varicaps allow an on chip
frequency pulling, controlled by the VCON input.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
VCON
120MHz to 200MHz Fundamental Mode Crystal.
Output range: 120MHz – 200MHz (no PLL).
Low Injection Power for crystal 50uW.
Complementary outputs: CMOS, PECL or LVDS.
Selectable OE Logic (enable high or enable low).
Integrated variable capacitors.
Supports 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
X+
X-
integrated
Oscillator
Amplifier
varicaps
Low Phase Noise VCXO (for 120-200MHz Fundamental Crystals)
w/
PLL520-20
OE
Q
Q
DIE CONFIGURATION
DIE SPECIFICATIONS
OUTPUT SELECTION AND ENABLE
Pad #9, 18, 25: Bond to GND to set to “0”, bond to VDD to set to “1”
No connection results to “default” setting through internal pull-up/-down.
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “1”
Y
OE_SELECT
X
1 (Default)
OUTSEL1
(Pad #9)
Pad #18
(0,0)
Pad dimensions
Reverse side
Logical states defined by CMOS levels if OE_SELECT is “0”
0
0
1
1
0
Thickness
26
27
28
29
30
31
Name
25
Size
1
24
2
23
Preliminary
1 (Default)
0 (Default)
3
OUTSEL0
OE_CTRL
(Pad #30)
Pad #25
22
4
21
0
1
0
1
0
1
65 mil
5
20
6
80 micron x 80 micron
PLL520-20
19
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
Tri-state
Output enabled
Output enabled
Tri-state
7
Selected Output
18
62 x 65 mil
8
Value
10 mil
GND
Rev 7/01/03 Page 1
12
11
10
17
16
15
14
13
9
State
(1550,1475)

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PLL520-20 Summary of contents

Page 1

... Integrated variable capacitors. Supports 3.3V-Power Supply. Available in die form. Thickness 10 mil. DESCRIPTIONS PLL520- VCXO IC specifically designed to pull high frequency fundamental crystals. Its design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability ...

Page 2

... Die at VCON = 1.65V L (xtal cut (xtal cut E SYMBOL CONDITIONS T From power valid VCXOSTB XTAL C /C < 250 VCON 3.3V at room temperature VCON = 0 to 3.3V 0V VCON 3.3V, -3dB PLL520-20 Preliminary MIN. MAX -0 -0 -65 150 S T -40 85 ...

Page 3

... At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz @10Hz @100Hz -75 -95 PLL520-20 Preliminary MIN. TYP. MAX. 100/80/40 3.13 3. ...

Page 4

... I OSD SYMBOL CONDITIONS R = 100 (see figure) f 50W 50W LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80 DIFF 20 PLL520-20 Preliminary MIN. TYP. MAX. 247 355 454 -50 50 1.4 1.6 0.9 1.1 1.125 1.2 1.375 -5.7 -8 MIN. TYP. MAX. 0.2 0.7 1.0 0.2 0.7 1.0 LVDS Switching Test Circuit ...

Page 5

... L DD (see figure SYMBOL CONDITIONS @20/80% - PECL t r @80/20% - PECL t f PECL Output Skew VDD OUT 2.0V 50% OUT DUTY CYCLE PLL520-20 Preliminary MIN. MAX. V – 1.025 DD V – 1.620 DD MIN. TYP. MAX. 0.6 1.5 0.5 1.5 t SKEW Rev 7/01/03 Page 5 UNITS V V UNITS ns ns ...

Page 6

... PLL520-20 Preliminary Rev 7/01/03 Page 6 ...

Page 7

... LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Preliminary PART NUMBER PLL520-20 DC TEMPERATURE C=COMMERCIAL PACKAGE TYPE D=DIE ...

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