ves1820x ETC-unknow, ves1820x Datasheet
ves1820x
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ves1820x Summary of contents
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... Cable demodulation. Cable modems MMDS (ETS 300-429). DESCRIPTION The VES1820X is a single chip channel receiver for 16, 32, 64, 128 and 256-QAM modulated signals. The device interfaces directly to the IF signal, which is sampled by a 9-bit AD converter. The VES1820X performs the clock and the carrier recovery functions ...
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This document is preliminary and is subject to change. Contact a comatlas representative to determine if this is the current information on this device. The information contained in this document has been carefully checked and is believed to be reliable. ...
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FIGURE 1 : FUNCTIONAL BLOCK DIAGRAM NCO 9 BASE-BAND IF ADC CONVERSION SACLK PLL XIN DE-INTERLEAVER comatlas reserves the right to make any change at anytime without notice. CLOCK AGC RECOVERY FILTERS CARRIER EQUALIZER BANK RECOVERY R. S. DECODER SDA ...
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TABLE 1 : ABSOLUTE MAXIMUM RATINGS Parameter Ambient operating temperature : Ta DC supply voltage DC Input voltage DC Input Current Lead Temperature Junction Temperature Stresses above the absolute maximum ratings may cause permanent damage to the device. Exposure to ...
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... The VES1820X implements a 9-bit analog to digital converter. No external voltage references are required to use the ADC. ½ PLL The VES1820X implements a PLL used as clock multiplier that the crystal can be low frequency (fundamental tone). ½ DOWN CONVERTER AND NYQUIST FILTERS The digital down converter performs the down conversion of the bandpass input signal into the 2 classical quadrature I & ...
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... To provide an initialization signal for the descrambler, the MPEG2 sync byte of the first transport packet is inverted from 47 "100101010000000". The descrambler can be inhibited. ½ INTERFACE The VES1820X integrates an I2C interface in slave mode. This I2C interface fulfills the Philips component I2C bus specification. comatlas reserves the right to make any change at anytime without notice. and are programmable through the I2C interface ...
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... I The CLR# input is asynchronous and active low, and clears the VES1820X. When CLR# goes low, the circuit immediately enters its RESET mode and normal operation will resume 4 XIN falling edges later after CLR# returned high. The I2C register contents are all initialized to their default values ...
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... MHz. I SADDR[1:0] are the 2 LSBs of the I2C address of the VES1820X. The MSBs are internally set to 00010. Therefore the complete I2C address of the VES1820X is (MSB to LSB SADDR[1], SADDR[0]. I/O SDA is a bidirectional signal the serial input/output of the I2C (5V) internal block ...
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SYMBOL PIN NUMBER CMCAP 85 RBIAS 82 VREF 88 VREFP 87 VREFM 86 CMO 84 CMI 83 VD1 81 VS1 80 VD2 94 VS2 93 VD3 89 VS3 90 VD4 95 DVCC 96 DGND 97 PLLGND 98 PLLVCC 99 PPLUS ...
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... VDD GND VCC VDi XIN XOUT POWER SUPPLIES VES1820X INPUTS INTERFACE TEST JTAG TESTO[16:0] VES1820X VSi 4 SACLK VAGC CTRL1 CTRL2 IT FEL OUTPUTS PSYNC UNCOR DEN OCLK 8 DO[7:0] TDO 80 VS1 VS4 ...
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TABLE 3 : PIN DESCRIPTION Pin Pin Name Direction 1 VDD - 2 XIN I 3 XOUT O 4 GND - 5 FI[ FI[ FI[ FI[ VDD - 10 GND - 11 ...
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S.A., 30 rue du Chêne Germain, BP 814, 35518 CESSON-SEVIGNE Cedex, FRANCE Phone : +33 (0 55, Fax : +33 (0 Internet: www.comatlas.fr comatlas reserves the right to make any change ...