LP3907SQ-JXQX NSC [National Semiconductor], LP3907SQ-JXQX Datasheet
LP3907SQ-JXQX
Related parts for LP3907SQ-JXQX
LP3907SQ-JXQX Summary of contents
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LP3907 Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface General Description The LP3907 is a multi-function, programmable Power Man- agement Unit, optimized for low power FPGAs, microproces- sors and DSPs. This device integrates two highly efficient ...
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Typical Application Circuit www.national.com FIGURE 1. Application Circuit 2 30017801 ...
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FIGURE 2. Application Circuit 3 30017802 www.national.com ...
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... Package received will have XXXX replaced with the specific part version ordered. Ordering Information Voltage Option Order Number Voltage “JXQX” LP3907SQ-JXQX Voltage “JXQX” LP3907SQX-JXQX Voltage “JXQX” LP3907SQ-JXQX** Voltage “JXQX” LP3907SQX-JXQX** ** For Forced PWM Buck Regulators. Default Voltage Options Regulator SW1 SW2 LDO1 LDO2 www ...
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Pin Descriptions Pin Pin Name I/O 1 VINLDO12 2 EN_T 3 NPOR O 4 GND_SW1 G 5 SW1 O 6 VIN1 7 ENSW1 8 FB1 9 GND_C G 10 AVDD 11 FB2 12 ENSW2 13 VIN2 14 SW2 O 15 ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications SDA, SCL IN GND to GND SLUG Power Dissipation (P ) D_MAX (T =85°C, T =125°C, )(Note ...
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Low Drop Out Regulators, LDO1 and LDO2 Unless otherwise noted 3. 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (Notes 10, ...
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I/O Electrical Characteristics Unless otherwise noted: Typical values and limits appearing in normal type apply for T type apply over the entire junction temperature range for operation, T Symbol Parameter V Input Low Level IL V Input High Level IH ...
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Typical Performance Characteristics — LDO Output Voltage Change vs Temperature (LDO1 3.6V 2.6V, 100mA load IN OUT Load Transient (LDO1 – 150 mA load IN OUT Line Transient (LDO1) 3.6 ...
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Enable Start-up time (LDO1) ) 0-3 2 OUT LDO Maximum Load V = 1.74V IN www.national.com , 1mA load 30017841 30017867 10 Enable Start-up time (LDO2) 0 – ...
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Typical Performance Characteristics — Bucks V = 2.8V to 5.5V 25° Shutdown Current vs. Temp Output Voltage vs. Supply Voltage (V = 1.8V) OUT Output Voltage vs. Supply Voltage (V 30017843 Output Voltage vs. Supply Voltage ...
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Typical Performance Characteristics — Buck1 V = 2.8V to 5.5V 25° OUT Efficiency vs Output Current (V =1.2V, L= 2.2µH —(Forced PWM mode) OUT Efficiency vs Output Current (V =1.2V, L= 2.2µH — PWM mode ...
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Typical Performance Characteristics — Buck2 V = 4.5V to 5.5V 25° 1.8V, 3. OUT Efficiency vs Output Current ( V =1.8V, L= 2.2µH —Forced PWM mode) OUT Typical Performance Characteristics — Buck2 V = ...
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Typical Performance Characteristics — Bucks V = 3.6V 25° 1.2V unless otherwise noted IN A OUT Load Transient Response V = 1.2V 300–500mA (PWM Mode) OUT LOAD Line Transient Response V = 3.6 – ...
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Start up into PFM Mode V = 1.2V, 30mA load OUT 30017862 Start up into PFM Mode V = 3.3V, 30mA load OUT 15 30017880 www.national.com ...
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DC/DC Converters OVERVIEW The LP3907 supplies the various power needs of the application by means of two Linear Low Drop Regulators (LDO1 and LDO2) and two Buck converters (SW1 and SW2). The table hereunder lists the output characteristics of the ...
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SW1, SW2: Synchronous Step- Down Magnetic DC/DC Converters FUNCTIONAL DESCRIPTION The LP3907 incorporates two high-efficiency synchronous switching buck regulators, SW1 and SW2, that deliver a con- stant voltage from a single Li-Ion battery to the portable system processors. Using a ...
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When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage to ~1.6% above the nominal PWM output voltage. If the load current should increase during PFM mode (see figure below) causing the ...
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FLEXIBLE POWER SEQUENCING OF MULTIPLE POWER SUPPLIES The LP3907 provides several options for power on sequenc- ing. The two bucks can be individually controlled with ENSW1 and ENSW2. The two LDOs can also be individually con- trolled with ENLDO1 and ...
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LP3907 Default Power-Up Sequence Power-On Timing Specification Symbol t Programmable Delay from EN_T assertion Programmable Delay from EN_T assertion Programmable Delay from EN_T assertion Programmable Delay from EN_T ...
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LP3907 Default Power-Off Sequence Symbol Description t Programmable Delay from EN_T deassertion Programmable Delay from EN_T deassertion Programmable Delay from EN_T deassertion Programmable Delay from EN_T deassertion to ...
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Flexible Power-On Reset (i.e., Power Good with delay) The LP3907 is equipped with an internal Power-On-Reset (“POR”) circuit which monitors the output voltage levels on bucks 1 and 2. The nPOR is an open drain logic output which The above ...
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Faults Occurring in Counter Delay After Startup The above timing diagram details the Power good with delay with respect to the enable signals EN1, and EN2. The RDY1, RDY2 are internal signals derived from the output of two com- parators. ...
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If the EN1 and RDY1 are initiated in normal operation, then NPOR is asserted and deasserted as explained above. In Case 1, we see that case where EN2 and RDY2 are initi- ated after triggered programmable delay. To prevent the ...
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Design Implementation of the Flexible Power-On Reset An internal Power-on reset of the IC is used with EN1, and EN2 to produce a reset signal (LOW) to the delay timer NPOR. EN1 and RDY1 or EN2 and RDY2 are used ...
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Compatible Serial Interface SIGNALS The LP3907 features compatible serial interface, using two dedicated pins: SCL and SDA for I spectively. Both signals need a pull-up resistor according to the I ...
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TRANSFERRING DATA Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse ...
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LP3907 Control Registers Register Register Read/ Address Name Write 0x02 ICRA R 0x07 SCR1 R/W 0x10 BKLDOEN R/W 0x11 BKLDOSR R 0x20 VCCR R/W 0x23 B1TV1 R/W 0x24 B1TV2 R/W 0x25 B1RC R/W 0x29 B2TV1 R/W 0x2A B2TV2 R/W 0x2B ...
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EN_DLY PRESET DELAY SEQUENCE AFTER EN_T ASSERTION EN_DLY<2:0> 000 001 010 011 100 101 110 111 BUCK AND LDO OUTPUT VOLTAGE ENABLE REGISTER (BKLDOEN) – 0X10 This register controls the enables for the Bucks and LDOs — Name ...
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BUCK1 TARGET VOLTAGE 1 REGISTER (B1TV1) – 0X23 This register allows the user to program the output target volt- age of Buck1. D7-5 — Name — Access Data Reserved Buck1 Output Voltage (V) 5’h00 5’h01 5’h02 5’h03 5’h04 5’h05 5’h06 ...
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BUCK1 RAMP CONTROL REGISTER (B1RC) - 0x25 This register allows the user to program the rate of change between the target voltages of Buck1. D7 Name - - - - Access - - - - Data Reserved Reset 0 D6-4 ...
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BUCK2 TARGET VOLTAGE 1 REGISTER (B2TV1) – 0X29 This register allows the user to program the output target volt- age of Buck2. D7-5 — Name — Access Data Reserved Buck2 Output Voltage (V) 5’h00 5’h01 5’h02 5’h03 5’h04 5’h05 5’h06 ...
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BUCK2 RAMP CONTROL REGISTER (B2RC) - 0x2B This register allows the user to program the rate of change between the target voltages of Buck2 D7 Name - - - - Access - - - - Data Reserved Reset 0 D6-4 ...
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BUCK FUNCTION REGISTER (BFCR) – 0x38 This register allows the Buck switcher clock frequency to be spread across a wider range, allowing for less Electro-mag- This register also allows dynamic scaling of the NPOR Delay Timing. The LP3907 is equipped ...
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LDO1 CONTROL REGISTER (LDO1VCR) – 0X39 This register allows the user to program the output target volt- age of LDO 1. D7-5 — Name LDO1_OUT — Access Data Reserved LDO1 Output voltage (V) 5’h00 5’h01 5’h02 5’h03 5’h04 5’h05 5’h06 ...
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Application Notes ANALOG POWER SIGNAL ROUTING All power inputs should be tied to the main VDD source (i.e. battery), unless the user wishes to power it from another source. (i.e. external LDO output). The analog VDD inputs power the internal ...
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Graph Showing a Typical Variation in Capacitance vs. DC Bias As shown in the graph, increasing the DC Bias condition can result in the capacitance value that falls below the minimum value given in the recommended capacitor specifications ta- ble. ...
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Capacitor Min Value C LDO1 C LDO2 C SW1 C SW2 Pullup Resistor Both SDA and SCL terminals need to have pullup resistors connected to VINLDO12 or to the power supply of the I master. The values ...
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Thermal Performance of the LLP Package The LP3907 is a monolithic device with integrated power FETs. For that reason important to pay special attention to the thermal impedance of the LLP package and to the PCB layout rules ...
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Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 0.8 mm 24-Pin LLP Package NS Package SQA24A For ordering, refer to Ordering Information table 40 ...
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Notes 41 www.national.com ...
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THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE ...